JP3271164B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a CC having a vertical overflow barrier control gate.
It is suitable for application to a D (charge coupled device) solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, a solid-state imaging device generally uses an interline transfer system. As shown in FIG. 3, a CCD solid-state imaging device according to this method has a photodiode I which accumulates signal charges corresponding to the amount of incident light.
.. Arranged for each pixel, and a vertical transfer CC for transferring signal charges accumulated in the photosensitive unit 2 in the vertical and horizontal directions, respectively.
D3 (V11 to V81, V12 to V82...) And horizontal transfer CCDs 4 (H1 to H4...).

As shown in FIG. 4, each photodiode 1 is surrounded by a horizontal isolation region 5 and a vertical isolation region 6 each of which is a high-concentration impurity implantation region of the same concentration.
These areas separate each photodiode 1 as a photoelectric conversion element from the adjacent vertical transfer CCD 3 and separate each adjacent photodiode 1 in the vertical direction.

In this type of CCD solid-state imaging device, a potential barrier is formed below the photodiode 1 by applying a constant potential to a semiconductor substrate, and each pixel is accumulated by increasing or decreasing the height of the potential barrier. The amount of signal charge that can be generated can be adjusted.

However, if a potential barrier is constantly generated, signal charges are continuously stored, so that the stored signal charges are once discharged at regular intervals. There is an electronic shutter as this function.

That is, in the CCD solid-state imaging device, during the period when the electronic shutter voltage ΔVSUB is off (this is the period when the potential applied to the semiconductor substrate is VSUB), the lower layer (P well) of the photodiode 1 made of a PN junction is used. The potential is raised to generate an overflow barrier 7 (solid line in FIG. 5), and a signal charge 8 is applied to a potential well generated between the overflow barrier 7 and the photodiode 1.
To accumulate. Subsequently, the CCD solid-state imaging device reads the accumulated signal charges to the vertical transfer CCD 3 and transfers the signal charges at a predetermined timing.

On the other hand, during the period when the electronic shutter voltage ΔVSUB is on (this is the period when the semiconductor substrate potential is VSUB + ΔVSUB), the CCD solid-state imaging device eliminates the potential peak in the P well (broken line in FIG. 5),
The electric charge stored until then is discharged to the semiconductor substrate side.

[0008]

By the way, with the miniaturization of the image pickup device, the area occupied by the photodiode 1 is becoming smaller today. Along with this, the junction capacitance between the vertical isolation region 6 and the P-well formed below each photodiode 1 becomes large, so that charging and discharging of signal charges cannot be quickly switched with a shutter voltage .DELTA.VSUB of the same magnitude as in the prior art. I'm getting better. For this reason, a large voltage must be used as the electronic shutter voltage ΔVSUB, which is a factor of increasing power consumption.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to propose a solid-state imaging device which can operate an electronic shutter with an electronic shutter voltage which is much lower than the conventional one. It is.

[0010]

According to the present invention, a plurality of photoelectric conversion elements 1 are arranged in a horizontal direction and a vertical direction, and a photoelectric conversion element array (1, 1, 2) is arranged in a vertical direction. ,...) And the vertical transfer region 3, the adjacent photoelectric conversion element rows (1, 1,...) And the vertical transfer region 3 are horizontally separated by a first separation region 5. , A vertical second isolation region 11 provided between the photoelectric conversion elements 1 of each photoelectric conversion element row (1, 1, ...).
The solid-state imaging device 1 separates the photoelectric conversion elements 1 adjacent to each other in the vertical direction, accumulates signal charges corresponding to the amount of incident light of the photoelectric conversion elements 1, and transfers the signal charges via the vertical transfer region 3.
0, the impurity concentration of the second isolation region 11 in the horizontal direction is lower than the impurity concentration of the first isolation region 5 in the vertical direction.
The junction capacitance between the photoelectric conversion element 1 and the well 12 disposed below the photoelectric conversion element 1 is set to be smaller than when the first and second impurity concentrations are the same.

[0011]

The impurity concentration of the first isolation region, which separates the plurality of photoelectric conversion elements in the vertical direction on the plane, of the second isolation region, which separates the plurality of photoelectric conversion elements in the horizontal direction on the plane, respectively. By setting the concentration sufficiently lower than the impurity concentration, the junction capacitance between the semiconductor layer 12 formed below each photoelectric conversion element 1 and the first isolation region 11 can be reduced.

As a result, even if the control pulse ΔVSUB applied to the semiconductor substrate 13 is small, the potential of the semiconductor layer 12 formed below the photoelectric conversion element 1 can be quickly switched and controlled. Can be further reduced.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

In FIG. 1 in which parts corresponding to those in FIG. 4 are assigned the same reference numerals, reference numeral 10 denotes a solid-state imaging device as a whole.
It has the same configuration except that the impurity concentration of the vertical isolation region 11 is formed to be sufficiently lower than the impurity concentration of the horizontal isolation region 5 (for example, about 10 ¹⁶ / cm ³ ).
Incidentally, the semiconductor imaging device 10 has a sectional structure (that is, II sectional structure) as shown in FIG. 2 in the vertical direction.

Here, junction capacitances formed between the P-type well 12 operating as the overflow barrier 7 and the vertical isolation region 11 are C1 and C2, respectively, and a junction capacitance formed between the P-type well 12 and the N-type semiconductor substrate 13 is C3. And other junction capacitances are omitted.

[0016] When the sum of junction capacitances C1, C2 and C3 generated at the bottom of each photodiode 1 this time and C _T, the value of the total junction capacitance C _T, the following equation

(Equation 1) Given by

Similarly, when the impurity concentration of the vertical isolation region 6 is almost the same as the impurity concentration of the horizontal isolation region 5 as in the conventional case, the impurity occurs between the P-type well 12 and the vertical isolation region 6 and the N-type semiconductor substrate 13. The junction capacitances are C10 and C
20 and C30, the total junction capacitance C corresponding to equation (1)
The value of _TO is

(Equation 2) Becomes

The operation of the solid-state imaging device 10 for turning on / off the electronic shutter in the above configuration will be described. The variation of the potential of the P-type well 12 when the shutter voltage .DELTA.VSUB is applied to the semiconductor substrate in the embodiment is .DELTA.V1, and the variation in the conventional example is .DELTA.V2. At this time, the variation ΔV1 according to the embodiment is expressed by the following equation.

(Equation 3) The variation ΔV2 according to the conventional example is given by the following equation:

(Equation 4) Given by

In the case of this embodiment, the vertical separation region 11
Is sufficiently lower than the impurity concentration in the vertical isolation region 6 of the conventional example, the junction capacitances C1, C2 and C10, C20 generated between the P-type well 12 and each region are expressed by the following equation.

(Equation 5) Holds.

The relation of the equation (5) is expressed by the equations (1) and (2).
By substituting into the equation, the solid-state imaging device 1 according to the embodiment
Towards the total junction capacitance C _T 0 is can be seen that less than the total junction capacitance C _TO of a conventional solid-state imaging device.

Therefore, by substituting this relationship into Equations (3) and (4), it can be seen that the denominator of the embodiment is smaller than that of the conventional example, and that the embodiment is more susceptible to the potential fluctuation of the substrate. This indicates that the potential of the P-type well 12 can be largely changed. That is, the shutter voltage Δ having a small amplitude
With V, the charge accumulation or discharge by the photodiode 1 can be quickly switched.

According to the above configuration, the impurity concentration to be implanted into the vertical isolation region 11 separating the photodiodes 1 adjacent in the vertical direction is sufficiently lower than the impurity concentration to be implanted into the horizontal isolation region 5. By doing so, the size of the junction capacitances C1 and C2 formed between the P-type well 12 operating as the overflow barrier 7 and the vertical isolation region 11 can be further reduced as compared with the related art.

As a result, even when the area occupied by the photodiode 1 is reduced, the P-type well 12 is affected by the junction capacitance generated between the P-type well 12 and the vertical isolation region 11.
Can be reduced, and the electronic shutter voltage ΔVSUB can be reduced as compared with the related art.

In the above embodiment, the case where the impurity concentration of the vertical isolation region 11 is lower than the impurity concentration of the horizontal isolation region 5 and the impurity concentration is about 10 ¹⁶ / cm ³ has been described. However, the present invention is not limited to this, and can be widely applied when the impurity concentration is approximately 10 ¹⁶ / cm ³ or less.

In the above-described embodiment, the case where the present invention is applied to a CCD solid-state image pickup device using an interline transfer method has been described. The present invention may be applied to a solid-state imaging device, and can be widely applied to a solid-state imaging device having a vertical overflow control gate.

[0026]

As described above, according to the present invention, a plurality of photoelectric conversion elements are vertically separated on a plane in comparison with an impurity concentration of a first separation region horizontally separated on a plane. By setting the impurity concentration of the isolation region 2 sufficiently low, the semiconductor layer formed under each photoelectric conversion element and the second
Junction capacitance between the isolation regions can be reduced. As a result, the electronic shutter voltage can be further reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a schematic plan view for describing a photoelectric conversion element and its separation region in a solid-state imaging device according to the present invention.

FIG. 2 is a partial cross-sectional view for describing a junction capacitance generated between a vertical isolation region and a semiconductor well.

FIG. 3 is a schematic plan view for describing a CCD solid-state imaging device using an interline transfer method.

FIG. 4 is a schematic plan view for explaining a photoelectric conversion element and its separation region in a conventional solid-state imaging device.

FIG. 5 is a potential diagram for describing an overflow barrier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Photodiode, 2 ... Photosensitive part, 3 ... Vertical transfer CCD, 4 ... Horizontal transfer CCD, 5 ... Horizontal separation area, 6, 11 ... Vertical separation area, 7 ... Overflow barrier, 8 ... ... signal charge, 10 ... solid-state imaging device, 12 ...
... P-type well, 13 ... Semiconductor substrate.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/148

Claims (2)

(57) [Claims] (1)Multiple photoelectric conversion elements in horizontal and vertical directions
Arrayed vertically and vertically with the photoelectric conversion element rows
Vertical first separation area provided between the direct transfer area and the direct transfer area
The photoelectric conversion element row and the vertical transfer area are separated by a region.
And between the photoelectric conversion elements of the respective photoelectric conversion element rows.
Vertical separation by the horizontal second separation region provided in
Separating the photoelectric conversion elements adjacent to each other in the
Accumulates signal charges according to the incident light amount of the
In a solid-state imaging device that transfers via a vertical transfer area, The impurity concentration of the second isolation region in the horizontal direction
Lower than the impurity concentration of the first isolation region in the vertical direction
The second separation region in the horizontal direction and the photoelectric conversion
The junction capacitance between the well and the well disposed under the switching element,
When the first and second isolation regions have the same impurity concentration
Smaller than Solid-state imaging device characterized by the following:
Place. 2. A solid-state imaging device according to claim 1, characterized in that said second impurity concentration 10 16 ^/ cm ³ or less.