JPS59208871A - Manufacture of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To enable to reduce the chip size by perfectly eliminating the dispersion of the channel length of a transfer gate region due to the shortage of mask alignment accuracy by a method wherein a vertical register and an impurity layer controlling the threshold voltages of the photoelectric conversion part and the transfer gate region are formed in self-alignment. CONSTITUTION:Leaving only the Si dioxide film 35 on a channel stop region 24 and a transfer gate region 20, the other Si dioxide film 30 is removed by etching with hydrofluoric acid series etchant. Next, after phosphorus ion implantation with said film 35 as a mask, an about 1,600Angstrom Si dioxide film 36 is formed by high temperature oxidizing treatment in an oxidizing atmosphere. Thereafter, the phosphorus ion-implanted in the former process is diffused to the depth of about 2mum by heat treatment, thus forming the N type layer serving as the buried channel of the vertical register 19 and the N type layer of the photoelectric conversion part 22 at the same time. By this process, it follows that the vertical register 19 and the photoelectric conversion part 22 are formed in so-called self- alignment, and accordingly the dispersion of the channel length of the transfer gate region 20 due to the shortage of mask alingment accuracy becomes perfectly eliminated.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a solid-state imaging device.

In recent years, with the rapid advancement of semiconductor and integrated circuit technology, the development of solid-state imaging devices has been strongly promoted. This solid-state image sensor is free from image distortion, afterimages, and burn-in, and is small, lightweight, and consumes low power, so it is being put into practical use as a replacement for image pickup tubes, mainly in home television cameras. However, in order to support high-definition television systems that will be put into practical use in the near future, the current 400
The number of pixels of about 500 x is still insufficient, and in order to miniaturize television camera optical systems and improve the yield of solid-state image sensing devices, it is necessary to further reduce the chip size compared to the current % inch system. In order to achieve this increase in the number of pixels and reduction in chip size, in addition to using a reduction projection exposure system in one step of photolithography, it is necessary to modify the manufacturing process itself to be suitable for miniaturization. There is.

FIG. 1 is a plan layout diagram for explaining an example of a solid-state image sensor. This solid-state image sensor is called an interline transfer type charge transfer image sensor, and it
A photoelectric conversion unit 11 for accumulating No. 5 charges, a transfer gate region 12 for reading out the signal charges accumulated in the photoelectric conversion unit 11 for each horizontal scanning period (field or frame), and readout signal charges. a vertical register 13 for transferring the signal charge in the vertical direction every horizontal scanning period (IH); a horizontal register 14 electrically coupled to one end of each vertical register for transferring the signal charge in the horizontal direction; An output circuit 15 for sequentially converting signal charges from the horizontal register 14 into voltage signals is connected to '41.

FIG. 2 is a sectional view taken along line AA' of the image sensor shown in FIG. Here, to simplify the explanation, the present image sensor is assumed to be an N-channel device. A charge transfer electrode 18 of a vertical register is provided on the main surface of the P-type substrate semiconductor 16 with an insulating layer 17 interposed therebetween. The vertical resistor 19 is constituted by a buried channel made of an N-type layer having a conductivity type opposite to that of the substrate semiconductor. Further, a P-type layer 21 having the same conductivity type as the substrate semiconductor is provided on the surface of the transfer gate region 20. Further, the charge transfer electrode 18 is arranged to cover the vertical register 19 and the transfer gate region 20. 22 is a photoelectric transformer section formed by forming a P-N junction with the substrate semiconductor;
Components other than the photoelectric conversion section 22 are shielded from light by a metal layer n.

Reference numeral 24 denotes a channel stop region with a high substrate impurity concentration, which separates each photoelectric conversion section 22 and vertical register 19 from each other.

Next, FIGS. 3 to 6 are diagrams for explaining the conventional process used to manufacture the solid-state image sensor shown in FIGS. 1 and 2. A' cross-sectional view is shown for each main process.

First, as shown in FIG. 3, a silicon dioxide film of approximately 1600^ was formed on the main surface of a 13Ω/my P-type silicon substrate 16 by high-temperature oxidation treatment in an oxidizing atmosphere, and then a known photoetching technique was applied. Then, the silicon dioxide film in the portion where the vertical register 19 will be formed is removed using a mask 25. Then, a mask 25 is formed. Next, using this mask 25, phosphorus is selectively implanted by ion implantation, and then high-temperature oxidation treatment is performed again in an oxidizing atmosphere to form a silicon dioxide film with a thickness of about 1600^ in the area. Afterwards, by high temperature treatment,
Phosphorus is diffused to a depth of about 2 μm to form an N-type layer that will become a buried channel of the vertical resistor 19.

Next, the silicon dioxide film 25 used as a mask for phosphorus implantation was removed using a hydrofluoric acid etching solution, and then the entire surface was thermally oxidized again.
A silicon dioxide film having a thickness of approximately 500 nm is formed over the entire main surface. A silicon nitride film 26 of about 1100^ thickness is then deposited by a known method using silane and ammonia, and only the silicon nitride film on the surface forming the channel stop region 24 is removed by a known plasma etching method. Using the film 26 as a mask, boron ions are implanted to form a channel stop region 24. Thereafter, by performing thermal oxidation, a silicon dioxide film 27 of approximately 8000^ thickness is formed on the surface of the channel stop region 24 not covered with the silicon nitride film 26 (FIG. 4).

Next, after removing the silicon nitride film 26 with an etching solution such as phosphoric acid, only the silicon dioxide film on the surface of the channel stop region 24 is left, and the rest is removed with a hydrofluoric acid-based etching solution, and then thermal oxidation is performed. A silicon dioxide film 28 of about 100 OA is formed. Then, by using a known photolithographic technique, the area other than the area where the transfer gate region 2 is to be formed is covered with a photoresist 29, and boron ions are implanted through the silicon dioxide film 28 using this mask 29 as a mask, and then transferred. A P-type layer 2 which controls the threshold voltage of the gate region 20 is formed (FIG. 5).

Next, the photoresist 2 used to form the P-type layer 21
9 is removed, a polycrystalline silicon film of about 6000^ is deposited on the entire surface by a known silane thermal decomposition method, and then phosphorus is diffused in order to make this polycrystalline silicon film conductive. Then, the polycrystalline silicon film in areas other than the charge transfer electrodes 18 is removed using known photolithographic techniques and plasma etching and tinting methods.

Next, using the polycrystalline silicon film forming the charge transfer electrode 18 as a mask, the portions of the silicon dioxide film 28 that are not covered with the polycrystalline silicon film are removed using a hydrofluoric acid-based enonening solution. Phosphorus is selectively implanted using the polycrystalline silicon film as a mask, and the photoelectric conversion section 22
An N-type layer is formed (FIG. 6).

Next, a silicon dioxide film with about 750 holes is formed on the surfaces of the charge transfer electrode 18 and the photoelectric conversion section 22 by thermal oxidation, and then a link glass film of about 11 μ7n is grown by vapor phase growth to form the insulating layer 17. Next, using a known photo-etching technique, a metal layer 23 for shielding parts other than the photoelectric conversion part 22 is formed.
(Figure 2).

According to the conventional manufacturing method of a solid-state image sensor, an N-type layer is first formed which will become the buried channel of the vertical register 9, and then a transfer gate area is formed by aligning the N-type layer here. 20 P-type layers 2I are formed, and then the N-type layer 2I is formed again.
The N-type layer of the photoelectric conversion section 22 (7) is formed in alignment with the mold layer. Therefore, the vertical register 19 and the photoelectric conversion section 2
In other words, the formation accuracy of the channel length of the transfer gate region 20 is determined by the mask alignment accuracy.

For example, the channel length on the mask of the transfer gate region 20 is set to 1
Assuming that the alignment accuracy for 5μm 1 mask is ±0.5μm,
The resulting channel length will vary between lO and 2.0μ7n. This causes the threshold voltage of the transfer gate region 20 to vary between approximately 3V and 6V from wafer to wafer, which greatly impedes the operation of the solid-state image sensor. Furthermore, since the P-type layer 21 and the photoelectric conversion section 22 in the transfer gate region 20 are formed through two mask alignment processes, if the mask alignment accuracy is ±0.5 μm, the minimum
．． An overlapping margin of 0 μm is essential. Along with this, the size per pixel inevitably increases, which becomes a major obstacle in increasing the number of pixels and reducing the size of the chimney size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solid-state image sensor that eliminates the above-mentioned drawbacks and allows for a large number of pixels and a reduction in chip-to-noise.

According to the present invention, a plurality of photoelectric conversion units are arranged in a matrix on a semiconductor substrate of a first conductivity type, and are of a second conductivity type opposite to the substrate, and a plurality of photoelectric conversion units of a second conductivity type opposite to the substrate, and A shift register section consisting of a plurality of rows of electric power transfer devices constituted by buried channels is provided between the shift register section corresponding to the photoelectric conversion section along the column direction, and the impurity d is of the first conductivity type. a transfer gate region consisting of a first semiconductor region with a low impurity concentration, and a second semiconductor region of the first conductivity type with a high impurity concentration, electrically separating the photoelectric conversion section and the shift register section from each other. In the manufacture of a solid-state image sensor configured as a channel stop region, after covering the yC city conversion portion and the shift/sister portion with silicon nitride, the transfer gate region and the channel are coated using the silicon nitride film as a mask. The first semiconductor region is formed in the stop region, and the transfer 'r
-1- After covering the region with a photoresist, the second semiconductor region is formed in the channel stop region using the silicon nitride film and the photoresist as a mask, and after removing the photoresist, the silicon nitride film is used as a mask. After removing the silicon nitride film, the second conductivity type is formed in the photoelectric conversion section and the shift register section using the silicon dioxide film as a mask, and then the second conductivity type is formed on the transfer gate region. There is obtained a method for soaking a solid-state image sensor in N, characterized by comprising the step of removing the silicon dioxide film.

Next, embodiments of the present invention will be described using the drawings.

For ease of explanation, the embodiment of the present invention is an N-channel device.

7 to 12 are diagrams for explaining the present invention in detail, and since the planar arrangement of the solid-state image sensing device manufactured according to the present invention is the same as that in FIG. 1, A'
Cross-sectional views are shown for each major process.

Components that are the same as those in FIGS. 2 to 6 are designated by the same numbers.

First, as shown in FIG. 7, a silicon dioxide film 30 of about 1,600^ was formed on the main surface of a 13Ω/my P-type silicon substrate 16 by high-temperature oxidation treatment in an oxidizing atmosphere, and then silane and ammonia were added. A silicon nitride film 31 is deposited using known methods. Next, a photoresist 32 is coated on this silicon nitride film 31, and a portion of the silicon nitride IJ film 31 where the channel stop region 24 and transfer gate region 20 are to be formed is formed using known photolithography and plasma etching techniques. Remove. Next, boron is accelerated with an energy of about 5 using the photoresist 32 as a mask.
Ion implantation is performed at 0 KeV and an ion implantation dose of 2.0 Is it the same as P-type layer 21?A
A P-type layer 33 of If is formed.

Next, using photolithography again, only the portion where the transfer gate region 20 will be formed is covered with a photoresist 34, and then, using the photoresists 32 and 34 as a mask, the holons are accelerated at an energy of about 100 KeV and an ion implantation dose of 2.
．． OxlO''/cIrL'' ions are implanted to form a channel stop region 24 with a high substrate impurity concentration.

Note that this channel stop region 24f was formed with P in the previous process.
Although a mold layer 33 has been formed, since the ion implantation dose value is one order of magnitude smaller than that in this step, its function as a channel stopper is determined by this step (FIG. 8).

Next, after removing the photoresists 32 and 34 used as masks for forming the channel stop region 24, approximately 800 OA is applied over the channel stop region 24 and transfer gate region 20 without thermal oxidation using the silicon nitride film 31 as a mask. A silicon dioxide film 35 is formed (FIG. 9).

Next, after removing the silicon nitride film 31 with an etching solution such as phosphoric acid, leaving only the silicon dioxide film 35 on the channel stop region 24 and transfer gate region 20, the other silicon dioxide film 30 is removed using a hydrofluoric acid etching solution. Remove with . Next, using the silicon dioxide film 35 as a mask, phosphorous is ion-implanted, and then high-temperature oxidation treatment is performed in an oxidizing atmosphere to form a silicon dioxide film 36 of about 160 OA. After that, by high temperature treatment, the phosphorus ion-implanted in the previous step is diffused to a depth of approximately 2 μm, and an N-type layer that will become the buried channel of the vertical resistor 19 and an N-type layer of the photoelectric conversion section 22 are simultaneously formed. do. Through this process, the vertical register 19 and the photoelectric conversion section 22 are formed by a so-called self-line, and the transfer gate region 2 due to insufficient mask alignment accuracy, which was a problem in the conventional manufacturing method.
There is no variation in the channel length of 0 (FIG. 10).

Next, the area other than the transfer gate region 20 is covered with a photoresist 37 using photolithography, and the silicon dioxide film 35 on the transfer gate region 20 is removed using the photoresist 37 as a mask (FIG. 11).

Next, after removing the photoresist 37, the silicon dioxide film 36 is removed using a filtrate-based etching solution, and then,
A silicon dioxide film 38 having a thickness of about 100 OA is formed by thermal oxidation ζ. Then, by the known pyrolysis method of silane, about 6
A 00OA polycrystalline silicon film is deposited over the entire wafer, and then phosphorous is diffused to make the polycrystalline silicon film conductive. Then, the polycrystalline silicon film in the area other than the charge transfer electrode (18) is removed using known photolithography and plasma etching. Next, about 75O by thermal oxidation
After forming the silicon dioxide film A, about 1.
A phosphorus gland having a thickness of 1 μ771 is grown, and together with the silicon dioxide films 35 and 38, an insulating film 17 is formed.

Next, using a known photo-etching technique, the area other than the photoelectrically affected area 22 is covered with a metal layer 23 for shielding light (FIG. 12).

As is clear from the above description of the embodiments, according to the present invention, the impurity layer for controlling the threshold voltage of the vertical register, photoelectric conversion section, and transfer gate region of the solid-state image sensor is 7"5T.
Since it can be formed in a so-called self-aligned manner, there is no fluctuation in the channel length of the transfer gate region due to the insufficient cross-sectional area of the mask 1, which was a problem in the conventional manufacturing process.

Furthermore, since there is no need for overlapping masks,
- The size per pixel can be reduced, and as a result, the number of pixels is increased and the size is reduced to aT*Q, which has a large effect.

Figure 1 shows an example of an interline transfer force type solid-state imaging device. 3 to 6 are cross-sectional views shown in the order of steps to illustrate an example of a conventional manufacturing method, and FIGS. 7 to 12 are sectional views for explaining the manufacturing method of the present invention. FIG.

11, 22... Optical IA converter, 12, 20... Transfer gate area, 13, 19... Vertical register, 1
4...Horizontal register, 15...Output circuit, 16...
- Substrate semiconductor, 17... Insulating layer, 18... Charge transfer electrode, 23... Metal layer, 2.1... Qi, Nels 1-7
area, 25, 27, 28, 3(+, 35
, :((i, 3F, 2fQ chloride film, 26
, 31...Yaka Sorikon Kin, 129 , 32, '
, i4.

37...Photo register.

Agent j Hei L Susumu Uchihara 1・' ・1,,
′、、、、= 1st overturn / I 2 I = 3 Evening j issue Ribi E ≥ 9 103 Figure 2 Tanon no -

Claims (1)

[Claims] A plurality of photoelectric conversion sections are arranged in a matrix on a semiconductor substrate of a first conductivity type, and are composed of a plurality of photoelectric conversion sections of a second conductivity type opposite to the substrate, and a implanted channel of the second conductivity type. A shift register section consisting of a plurality of rows of charge transfer devices, and a shift register section corresponding to the light 1 ((, dl transfer section) along the column direction; a transfer gate region consisting of a first semiconductor region with a low impurity concentration, and a second semiconductor region of the first conductivity type with a high impurity concentration, electrically isolating the photoelectric conversion section and the shift register section from each other. In manufacturing solid-state imaging devices composed of channel stop chain acids,
After covering the photoelectric conversion section and the shift register section with a silicon nitride film, the first semiconductor region is formed in the transfer gate region and the channel stop region by masking the silicon nitride film, and the first semiconductor region is formed in the transfer gate region (ijJ region). forming the second semiconductor region in the channel/tube region using the silicon nitride film and the photoresist as a mask, and removing the photoresist and using the silicon nitride film as a mask; After forming a silicon dioxide film and removing the silicon nitride film, the silicon dioxide film is used as a mask to cover the photoelectric conversion section and the shift register section.
1. A method for manufacturing a solid-state sensor one-station device, comprising the steps of: forming a conductivity type, and then removing the silicon dioxide film on the transfer gate region.