JPH0276850U - - Google Patents
Info
- Publication number
- JPH0276850U JPH0276850U JP15758288U JP15758288U JPH0276850U JP H0276850 U JPH0276850 U JP H0276850U JP 15758288 U JP15758288 U JP 15758288U JP 15758288 U JP15758288 U JP 15758288U JP H0276850 U JPH0276850 U JP H0276850U
- Authority
- JP
- Japan
- Prior art keywords
- mount
- circuit pattern
- internal leads
- chip
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005611 electricity Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本願考案の一実施例の断面図、第２図
は平面図、第３図は他の実施例の断面図、第４図
は従来例の断面図である。
１……マウント部、３……チツプ、４……内部
リード、６……回路パターン、７……電子部品、
８……リード足。
FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a plan view, FIG. 3 is a sectional view of another embodiment, and FIG. 4 is a sectional view of a conventional example. 1...Mount part, 3...Chip, 4...Internal lead, 6...Circuit pattern, 7...Electronic component,
8...Lead foot.
Claims (1)
リードを上記マウント部の上面に導出するととも
に、マウント部の上面に上記内部リードと導通す
る回路パターンを形成してこれに所定のチツプ型
電子部品を面実装する一方、上記マウント部の側
部に、上記回路パターンの適部に導通する複数本
のリード足を取付けたことを特徴とする、集積回
路装置。 Internal leads communicating with the chip sealed in the mount are led out to the top of the mount, and a circuit pattern is formed on the top of the mount to be electrically connected to the internal leads, and a predetermined chip-type electronic component is mounted on this. What is claimed is: 1. An integrated circuit device which is surface-mounted and has a plurality of lead legs attached to a side of the mount portion to conduct electricity to appropriate portions of the circuit pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15758288U JPH0276850U (en) | 1988-12-01 | 1988-12-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15758288U JPH0276850U (en) | 1988-12-01 | 1988-12-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0276850U true JPH0276850U (en) | 1990-06-13 |
Family
ID=31437149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15758288U Pending JPH0276850U (en) | 1988-12-01 | 1988-12-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0276850U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033457B2 (en) * | 1981-09-22 | 1985-08-02 | カワサキ機工株式会社 | Tea processing method and tea processing device |
-
1988
- 1988-12-01 JP JP15758288U patent/JPH0276850U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033457B2 (en) * | 1981-09-22 | 1985-08-02 | カワサキ機工株式会社 | Tea processing method and tea processing device |