JPH0276052A - Bus extending device - Google Patents

Bus extending device

Info

Publication number
JPH0276052A
JPH0276052A JP22896288A JP22896288A JPH0276052A JP H0276052 A JPH0276052 A JP H0276052A JP 22896288 A JP22896288 A JP 22896288A JP 22896288 A JP22896288 A JP 22896288A JP H0276052 A JPH0276052 A JP H0276052A
Authority
JP
Japan
Prior art keywords
signal
interrupt request
main body
extending device
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22896288A
Other languages
Japanese (ja)
Inventor
Shuhei Morikawa
守川 修平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22896288A priority Critical patent/JPH0276052A/en
Publication of JPH0276052A publication Critical patent/JPH0276052A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of interruption request signal lines to connect a bus extending device and a processor main body by sending a time slot signal from an subsidiary control circuit, which is mounted to the processor main body, to the bus extending device and summurizing plural interruption requesting signals, which are generated in the internal part of this bus extending device, one signal synchronously with the time slot signal by a control circuit in the bus extending device side. CONSTITUTION:A bus extending device 21 is provided to extend the bus of the processor main body. Namely, when the interruption requesting signals being outputted from input and output controllers 2 and 3, which are mounted to a bus extending device 21, are received by a bus 4 of the bus extending device 21, a multiplexing control circuit 22 summurizes the signals to one interruption requesting signal synchronously with the time slot signal and an interruption requesting signal driver circuit 23 outputs the requesting signal to a signal cable 24 as the multiplexed interruption requesting signal. Thus, the number of the interruption requesting signal lines to connect the bus extending device 21 and a processor main body 8 can be decreased.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、パーソナルコンピュータ及び端末装置等の
処理装置本体に接続するパス拡張装置に間するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a path extension device connected to a processing device main body such as a personal computer and a terminal device.

[従来の技術] 第3図は従来のパス拡張装置と処理装置本体との接続関
係図である。図において、lはパス拡張装置、2はパス
拡張装置1に実装された人出力制御装置(IOC−1)
、3はパス拡張装置1に実装されたn番目の人出力制御
装置(IOC−n)、4はパス拡張装置1のパス、5は
割込み要求信号ドライバ回路、6は割込み要求信号以外
のパス制御信号発生回路、7は信号ケーブル、8はデー
タの処理装置本体、9は割込み要求信号レシーバ回路、
10は割込み要求信号以外のパス制御信号発生回路、1
1は処理装置本体8のパス、】2は割込み制御回路(I
T)、13はシステム全体を制御する中央処理装置(C
PU)である。
[Prior Art] FIG. 3 is a diagram showing the connection relationship between a conventional path extension device and a processing device main body. In the figure, l is the path extension device, and 2 is the human output control device (IOC-1) installed in the path extension device 1.
, 3 is the n-th human output control device (IOC-n) mounted on the path extension device 1, 4 is the path of the path extension device 1, 5 is the interrupt request signal driver circuit, and 6 is the path control other than the interrupt request signal. A signal generation circuit, 7 a signal cable, 8 a data processing device main body, 9 an interrupt request signal receiver circuit,
10 is a path control signal generation circuit other than interrupt request signals;
1 is the path of the processing device main body 8, ]2 is the interrupt control circuit (I
T), 13 is a central processing unit (C) that controls the entire system.
PU).

第4図は従来例による割込み要求信号の発生タイミング
を示す図である。
FIG. 4 is a diagram showing the timing of generation of an interrupt request signal according to a conventional example.

次に、上記従来のパス拡張装置と処理装置本体との動作
について説明する。パス拡張装置lに実装された入出力
制御H置2及び3から出力された割込み要求信号はパス
′拡張装置1のパス42割込み要求信号ドライバ回路5
.信号ケーブル7を経由して処理装置本体8に達し、割
込み要求信号レシーバ回路9でバッファされた後、処理
装置本体8のパス11に割込み要求信号を伝える。処理
装置本体8のパス11には割込み要求信号を受ける割込
み制御回路12が接続されており、割込み要求信号のL
owからHighへのレベル変化を検出して、人出力制
御装置2及び3の1番目からn番目の割込み要求信号を
ベンディングし、中央処理装置13へ割込み要求を出す
Next, the operation of the conventional path extension device and the main body of the processing device will be explained. The interrupt request signal output from the input/output control units 2 and 3 mounted in the path extension device 1 is sent to the path 42 interrupt request signal driver circuit 5 of the path extension device 1.
.. The interrupt request signal reaches the processing device main body 8 via the signal cable 7, is buffered by the interrupt request signal receiver circuit 9, and then is transmitted to the path 11 of the processing device main body 8. An interrupt control circuit 12 that receives an interrupt request signal is connected to the path 11 of the processing device main body 8.
It detects a level change from OW to High, bends the first to nth interrupt request signals of the human output control devices 2 and 3, and issues an interrupt request to the central processing unit 13.

第4図には、人出力制御装置(IOC−1)2及び<丁
0C−n)3から発生した割込み要求信号が、そのまま
処理装置本体8のパスll上を経由して中央処理装置(
CPU)13へ達するタイミングの概念が示されている
In FIG. 4, an interrupt request signal generated from the human output control device (IOC-1) 2 and <0C-n) 3 is directly passed through the path 11 of the processing device main body 8 to the central processing unit (
The concept of the timing of reaching the CPU 13 is shown.

[発明が解決しようとする課題] 上記従来のパス拡張装置は以上のように構成されている
ので、多数の割込み要求レベルを使用している人出力制
御装置を収容するためには、多数の拡張された割込み要
求レベルに1対1で対応したハードウェアを持つ必要が
あり、パス拡張装置で使用する割込み要求レベルは数を
制限することが必要となり、また多数の割込み要求レベ
ルを使用可能とするには、装置の製造原価が高くなるな
どの問題点があった。
[Problems to be Solved by the Invention] Since the conventional path extension device described above is configured as described above, in order to accommodate a human output control device that uses a large number of interrupt request levels, a large number of extensions are required. It is necessary to have hardware that corresponds one-to-one to the interrupt request levels that have been received, and it is necessary to limit the number of interrupt request levels used by the path expansion device, and it is also necessary to make it possible to use a large number of interrupt request levels. However, there were problems such as an increase in the manufacturing cost of the device.

この発明は上記のような問題点を解決するためになされ
たもので、処理装置本体で使用可能としている割込み要
求レベルの数を減少することなく、信号線を減少させる
ことができるパス拡張装置を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and it provides a path expansion device that can reduce the number of signal lines without reducing the number of interrupt request levels that can be used in the main body of the processing device. The purpose is to obtain.

[課題を解決するための手段] この発明に係るパス拡張装置は、処理装置本体に実装し
た付属制御回路からタイムスロット信号をパス拡張装置
に送出し、このパス拡張装置の内部で発生した複数の割
込み要求信号を上記タイムスロット信号にパス拡張装置
側の制御回路で同期して一本の信号に集約し、パス拡張
装置と処理装置本体との間を接続する割込み要求信号線
の本数を減少させたものである。
[Means for Solving the Problems] A path extension device according to the present invention sends a time slot signal to the path extension device from an auxiliary control circuit mounted on a processing device main body, and transmits a time slot signal to the path extension device by transmitting a time slot signal to the path extension device. The interrupt request signal is synchronized with the time slot signal by the control circuit on the path extension device side and aggregated into a single signal, thereby reducing the number of interrupt request signal lines connecting the path extension device and the processing device main body. It is something that

[作用] この発明におけるパス拡張装置は、パス拡張装置の内部
で発生した割込み要求信号は、処理装置本体側に実装さ
れた付属制御回路とパス拡張装置側に実装された制御回
路により、信号ケーブル上で時分割信号に変換され、パ
ス拡張装置と処理装置本体との間を伝播する。
[Function] In the path extension device of the present invention, an interrupt request signal generated inside the path extension device is transmitted through a signal cable by an attached control circuit mounted on the processing device main body side and a control circuit mounted on the path extension device side. The signal is then converted into a time-division signal and propagated between the path extension device and the processing device main body.

[実施例] 第1図はこの発明の実施例であるパス拡張装置と処理装
置本体との接続関係図で、第3図と同一符号は同−又は
相当部分を表示している。図において、21はこの発明
による機能を備えたパス拡張装置、22はパス拡張装置
21の内部で発生する複数の割込み要求信号を一本の信
号線に集約する多重化制御回路、23は割込み要求信号
ドライバ回路、24は処理装置本体8とパス拡張装置2
1を接続する信号ケーブル、25は多重化された割込み
要求信号を受信するレシーバ回路とタイムスロット信号
の発生回路からなる割込み要求受信回路、26は多重化
された割込み要求信号を元の割込み要求信号に復元する
復元回路である。
[Embodiment] FIG. 1 is a diagram showing the connection relationship between a path extension device and a processing device main body according to an embodiment of the present invention, and the same reference numerals as in FIG. 3 indicate the same or corresponding parts. In the figure, 21 is a path extension device equipped with a function according to the present invention, 22 is a multiplexing control circuit that aggregates a plurality of interrupt request signals generated inside the path extension device 21 into one signal line, and 23 is an interrupt request signal line. Signal driver circuit, 24 indicates processing device main body 8 and path expansion device 2
1, 25 is an interrupt request receiving circuit consisting of a receiver circuit that receives multiplexed interrupt request signals and a time slot signal generation circuit, and 26 is a signal cable that connects multiplexed interrupt request signals to the original interrupt request signal. This is a restoration circuit that restores

第2図はこの発明の実施例による割込み要求信号の発生
タイミングを示す図である。
FIG. 2 is a diagram showing the timing of generation of an interrupt request signal according to an embodiment of the present invention.

次に、上記この発明の実施例であるパス拡張装置と処理
装置本体との動作について説明する。パス拡張装置21
に実装された人出力制御装置2及び3から出力された割
込み要求信号をパス拡張装置21のパス4により受ける
と、多重化制御回路22はタイムスロット信号に同期し
て一本の割込み要求信号に集約し、割込み要求信号ドラ
イバ回路23が信号ケーブル24へ多重化された割込み
要求信号として出力する。
Next, the operation of the path extension device and the processing device main body according to the embodiment of the present invention will be explained. Path extension device 21
When the path 4 of the path extension device 21 receives the interrupt request signals output from the human output control devices 2 and 3 mounted in The interrupt request signal driver circuit 23 outputs the signal to the signal cable 24 as a multiplexed interrupt request signal.

上記多重化された割込み要求信号は割込み要求受信回路
25にて受信され、復元回路26にて、タイムスロット
信号によりパス拡張装置21の内部で発生した割込み要
求信号があたかも処理装置本体8の内部で発生した割込
み要求信号であるかのごとく、割込み制御回路12に伝
達され、この割込み制御回路12にて第2図に示すIR
QIからI RQnまでの割込み要求信号として認識さ
れ、その結果、中央処理装置13へ割込み要求が伝達さ
れる。
The multiplexed interrupt request signal is received by the interrupt request receiving circuit 25, and the restoring circuit 26 converts the interrupt request signal generated inside the path extension device 21 by the time slot signal to the inside of the processing device main body 8. It is transmitted to the interrupt control circuit 12 as if it were a generated interrupt request signal, and the interrupt control circuit 12 outputs the IR as shown in FIG.
It is recognized as an interrupt request signal from QI to IRQn, and as a result, the interrupt request is transmitted to the central processing unit 13.

第2図には、人出力制御装置(IOC−1)2及び(I
OC−n)3から発生した割込み要求信号が、信号ケー
ブル24上をタイムスロット信号に同期して割込み要求
信号が多重化される状態を示している。
Figure 2 shows the human output control device (IOC-1) 2 and (IOC-1)
This shows a state in which the interrupt request signal generated from OC-n) 3 is multiplexed on the signal cable 24 in synchronization with the time slot signal.

かりに、16種類の割込み要求信号を1本の多重化され
た割込み要求信号に集約する例を考えると、タイムスロ
ット信号として4本の制御信号が増加するが、16本の
割込み要求信号線は単に1本に集約できる。
If we consider an example in which 16 types of interrupt request signals are combined into one multiplexed interrupt request signal, four control signals will be added as time slot signals, but the 16 interrupt request signal lines will simply be Can be consolidated into one book.

なお、上記実施例では割込み要求信号について多重化す
る例につき説明したが、DMA (d i rect 
 memory  access−直接メモリアクセス
)要求信号や他のステータス信号であっても良く、上記
実施例と同様の効果を奏する。
Incidentally, in the above embodiment, an example was explained in which the interrupt request signal is multiplexed, but DMA (d i rect
A request signal (memory access (direct memory access)) or other status signal may be used, and the same effect as in the above embodiment can be achieved.

[発明の効果コ 以上のように、この発明のパス拡張装置によれば、処理
装置本体に実装した付属制御回路からタイムスロット信
号をパス拡張装置に送出し、このパス拡張装置の内部で
発生した複数の割込み要求信号を上記タイムスロット信
号にパス拡張装置側の制御回路で同期して一本の信号に
集約し、パス拡張装置と処理装置本体との間を接続する
割込み要求信号線の本数を減少させた構成としたので、
装置が安価に構成でき、また拡張性の高いパス拡張装置
が得られるという優れた効果を奏する。
[Effects of the Invention] As described above, according to the path extension device of the present invention, a time slot signal is sent to the path extension device from the attached control circuit mounted on the processing device main body, and time slot signals generated inside the path extension device are transmitted to the path extension device. A control circuit on the path extension device side synchronizes multiple interrupt request signals with the above time slot signal and aggregates them into a single signal, thereby reducing the number of interrupt request signal lines connecting the path extension device and the processing device main body. Since the configuration has been designed to reduce the number of
This has excellent effects in that the device can be constructed at low cost and a path extension device with high expandability can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例であるパス拡張装置と処理装
置本体との接続関係図、第2図はこの発明の実施例によ
る割込み要求信号の発生タイミングを示す図、第3図は
従来のパス拡張装置と処理装置本体との接続関係図、第
4図は従来例による割込み要求信号の発生タイミングを
示す図である。 図において、1,21・・・パス拡張装置、2,3・・
・人出力制御装置(IOC−1)、  (IO(、−n
)、4・・・パス拡張装置1のパス、5・・・割込み要
求信号ドライバ回路、6・・・パス制御信号発生回路、
7゜24・・・信号ケーブル、8・・・処理装置本体、
9・・・割込み要求信号レシーバ回路、10・・・パス
制御信号発生回路、11・・・処理装置本体8のパス、
12・・・割込み制御回路(IT)、13・・・中央処
理装置(CPU)、22・・・多重化制御回路、23・
・・割込み要求信号ドライバ回路、25・・・割込み要
求受信回路、26・・・復元回路 である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a diagram showing the connection relationship between a path extension device and a processing device main body according to an embodiment of the present invention, FIG. 2 is a diagram showing the generation timing of an interrupt request signal according to an embodiment of the present invention, and FIG. 3 is a diagram showing a conventional FIG. 4 is a diagram showing the connection relationship between the path extension device and the processing device main body, and is a diagram showing the timing of generation of an interrupt request signal according to a conventional example. In the figure, 1, 21... path extension device, 2, 3...
・Human output control device (IOC-1), (IO(,-n
), 4... Path of path extension device 1, 5... Interrupt request signal driver circuit, 6... Path control signal generation circuit,
7゜24...Signal cable, 8...Processing device main body,
9... Interrupt request signal receiver circuit, 10... Path control signal generation circuit, 11... Path of processing device main body 8,
12... Interrupt control circuit (IT), 13... Central processing unit (CPU), 22... Multiplexing control circuit, 23.
. . . interrupt request signal driver circuit, 25 . . . interrupt request receiving circuit, 26 . . . restoring circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 処理装置本体のパスを拡張するパス拡張装置と、このパ
ス拡張装置の内部に実装した制御装置が発生する割込み
要求信号を複数まとめて1本の信号とする制御回路と、
伝達された信号から複数の割込み要求信号を復元する上
記処理装置本体に実装した付属制御回路とを備えたこと
を特徴とするパス拡張装置。
a path extension device for extending a path of a processing device main body; a control circuit for combining a plurality of interrupt request signals generated by a control device mounted inside the path extension device into one signal;
A path expansion device comprising: an auxiliary control circuit mounted on the processing device main body for restoring a plurality of interrupt request signals from transmitted signals.
JP22896288A 1988-09-13 1988-09-13 Bus extending device Pending JPH0276052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22896288A JPH0276052A (en) 1988-09-13 1988-09-13 Bus extending device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22896288A JPH0276052A (en) 1988-09-13 1988-09-13 Bus extending device

Publications (1)

Publication Number Publication Date
JPH0276052A true JPH0276052A (en) 1990-03-15

Family

ID=16884593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22896288A Pending JPH0276052A (en) 1988-09-13 1988-09-13 Bus extending device

Country Status (1)

Country Link
JP (1) JPH0276052A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008310826A (en) * 1995-07-11 2008-12-25 Nokia Corp Handling interrupt in synchronous environment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008310826A (en) * 1995-07-11 2008-12-25 Nokia Corp Handling interrupt in synchronous environment

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