JPH0275223A - Control system for pll circuit - Google Patents

Abstract

PURPOSE:To improve high speed performance for establishing synchronization and stability in a steady-state by varying a conversion gain coefficient of a phase comparator section in multistage from a larger to a smaller coefficient according to the elapse of time and varying the loop gain of a loop filter section from a smaller to a larger gain according to the change in the conversion gain coefficient. CONSTITUTION:The system consists of a phase comparator section 1, a loop filter section 2 and a digital VCO section 3. The conversion gain coefficient K1 of a multiplier 1-2 in the phase comparator section 1 is changed from a larger value to a smaller value as the elapse of time and the loop filter 2 is provided with a multiplier 2-3 and an adder 2-4 to change the loop gain K2 from a small to a large value corresponding to the change in the conversion gain coefficient K1. Thus, the high speed performance for establishing synchronization and the stability in the steady-state obtained by controlling the gain conversion characteristic K1 are further improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control system for a PLL (phase locked loop) circuit.

(Prior Art) FIG. 2 is a block diagram showing an example of a PLL circuit using a conventional control method. Also DSP (Digital Signal Pro)
This is realized by digital processing using cessor).

In FIG. 2, the phase comparator section 5 consists of a binary quantization phase comparator (BPD) 5-1 and a multiplier 5-2, and the loop filter section 6 consists of an adder 6-1 and a sampling period T. The digital 760 section 7 includes an adder 7-1, a delay circuit (Z=) 6-2, and a delay circuit (Z=) 6-2.
Z) 7-3, a sine value generation circuit (SIN) 7-4 that outputs the sine value using the input as an argument, and a VCO free-running frequency f. It is composed of a circuit (not shown) that generates a phase advance angle 2πfoT during the sampling period T at . Further, a digital signal sampled at a sampling period T is input to the PLL input terminal 8.

To explain the operation of the PLL circuit shown in FIG. 2, in the phase comparator section 5, the input signal from the PLL input terminal 8 and the digital
The phase with ■CO output from section 7 is compared, and if the input signal is ahead of the VCO output in phase, +1'''
However, if the phase is delayed, -1'' is output.

The output II+II+ or -1'' is similarly multiplied by a conversion gain coefficient K (constant) by a multiplier 5-2 of the phase comparator section 5, and outputted as phase error information. The effect of noise is removed from the output from the multiplier 5-2 by the loop filter section 6. In the digital 700 section 7, the output from the loop filter section 6 and the vCO free running frequency f
Phase advance angle 2πf during sampling period T at c
The phase at time t is created from oT and the phase at time (t-T), and this is used as an argument to generate a sine value.

The generated sine value is input to the binary quantization phase comparator (BPD) 5-1 of the phase comparator section 5 as a VCO output.

Through the above operations, the frequency and phase of the input signal input from the PLL input terminal 8 and the frequency and phase of the VCO output from the digital 700 section 7 are synchronized.

(Problem to be Solved by the Invention) However, in the above control method, if the conversion gain coefficient K of the phase comparator section 5 is increased in order to establish high-speed synchronization, the phase error in the steady state, that is, the stability deteriorates, and vice versa. When the conversion gain coefficient K is made smaller in order to improve stability in a steady state, the establishment of synchronization is delayed, resulting in a problem that it is not possible to achieve both high speed of establishing synchronization and stability in a steady state. .

An object of the present invention is to eliminate the above-mentioned problems and provide a control system for PT and L circuits that is excellent in both high-speed synchronization establishment and stability in a steady state.

(Means for Solving the Problems) The present invention provides a control system for a PLL circuit including a phase comparator section, a loop filter section, and a voltage controlled oscillator section. This is a control method for a PLL circuit, characterized in that the loop gain of the loop filter section is controlled from small to large according to the change in the conversion gain coefficient, and the loop gain of the loop filter section is controlled from small to large in accordance with the change in the conversion gain coefficient.

(Function) At the initial stage of PLL operation, synchronization is quickly established by setting the value of the conversion gain coefficient of the phase comparator section to a positive value, and in a steady state, stable operation is achieved by making the value of the conversion gain coefficient small. is ensured. Furthermore, the value of the conversion gain coefficient can be changed by controlling the value of the loop key of the loop filter section for removing the influence of noise from small to small and correspondingly from small to large. The high speed of synchronization establishment and the stability in steady state obtained by this control are made even more effective.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, in which the phase comparator section l, similar to the conventional PLL circuit shown in FIG.
It consists of a loop filter section 2 and a digital 760 section 3, but the difference is that the conversion gain coefficient of the multiplier 1-2 in the phase comparator section 1 is changed to a value of 1 over time, and the loop filter section The difference is that a multiplier 2-3 and an adder 2-4 are newly provided in 2, and the loop key thereof is changed in accordance with a change of 1 in the conversion gain coefficient.

Note that the PLL circuit shown in FIG. 1 is a DSP (Digit
This can be realized as digital processing using the AlSignalProcessor).

The operation of this embodiment will be explained below based on FIG.

Binary quantization phase comparator (BPD) in phase comparator section 1
) 1-1 receives an input signal via the PLL input terminal 4 and also receives a vCO output signal from the digital 700 section 3. The input signal is a digital signal sampled at a sampling period T, and the VCO output signal is also output at every period T. The binary quantization phase comparator (
BPD) 1-1 compares the phase of the input signal and the vCO output signal, and if the phase of the input signal is ahead of the VCO output signal, it is +1''', and if it is behind, it is II-.
Output II+. The output '+1' or l, +1 is multiplied by 1 to the conversion gain coefficient by the subsequent multiplier 1-2,
It is output to the roof 0 filter section 2 as phase error information.

The PLL circuit is required to quickly establish synchronization in the initial stage of operation, and to operate stably after synchronization is established.

In this embodiment, the conversion gain coefficient is controlled to a value of 1 and set to a large value at the start of synchronization to speed up synchronization establishment, and as time passes, it is controlled to change from dog to small in multiple stages to maintain a steady state. In this state, the conversion gain coefficient is kept at a small value of 1 to reduce the phase error and improve stability. This allows for high speed synchronization establishment and high stability in steady state at the same time.

The output of the phase comparator section 1 is inputted to the digital 700 section 3 after the effects of noise are removed by the loop filter section 2 .

In the loop filter unit 2, the multiplier of the multiplier 2-3 is set to 2, that is, the loop gain is set to 2 as the conversion gain coefficient changes from 1 to small as time passes so as to satisfy equation (1). Small → controlled by dog.

FIG. 3 is a diagram for explaining the effect of the value of 2 on the operation of the PLL circuit, (a) the operation when 2 is small, and (b) the operation when 2 is small. are shown respectively. When K2 is small, as shown in (a), the speed of establishing synchronization is fast, but stability in the steady state is lacking.

On the other hand, when K2 is a dog, as shown in (b), the stability in the steady state is excellent, but the speed of establishing synchronization is slow. Therefore, in this embodiment, when synchronization is established, two
By controlling 2 to a small value, the speed of synchronization establishment is increased, and as time passes, the value of 2 is reduced in multiple steps, and in the steady state, high stability is achieved by controlling 2 to a large value. It is secured. In this embodiment, the conversion gain coefficient in the phase comparator section 1 described above is controlled by 1, and the multiplier 2-3 in the loop filter section 2 is controlled by 2 to satisfy equation (1). By executing the K1 control at the same time, the effect of the K1 control is combined with the effect of the K2 control, and a better effect can be obtained. This simultaneously achieves stability in a steady state.

The output of the loop filter section 2 is input to the digital 700 section 3, and the adder 3-1 converts the output to the vCO free-running frequency f.

The phase advance angle 2πfc during the sampling period T in
T and further added to adder 3-1 and delay circuit (Z-1)
3-3, the phase is added to the phase at the time before the time T, and the sine value generation circuit (SIN) uses the result as an argument.
) 3-4 generates a sine value and outputs it as a digital vCO. In addition, sine value generation circuit (SIN) 3-4
is realized by referring to and extracting a sine value table created on the ROM of the DSP according to the value of the argument.

FIG. 4 shows control examples 1 and 2 when the PLL circuit shown in FIG. 1 is applied as an input echo signal offset frequency absorption circuit to the V32 modem echo canceller section. The sampling period T is 1/17.2kHz (s
ee), the free running frequency fc is 1800 Hz. According to this control example, due to the application of the PLL circuit,
No deterioration in S/N vs. bit error of the modem was observed, and the PL
It is shown that the L circuit operates stably in a steady state.

(Effects of the Invention) As described above in detail, according to the present invention, the PLL
In the circuit, the conversion gain coefficient of the phase comparator section is changed in multiple steps from large to small as time passes, and the loop gain of the Luino filter section is changed from small to large according to the change in the conversion gain coefficient. , it was possible to achieve both high-speed synchronization establishment and stability in a steady state when establishing PLL synchronization.

It can be applied to a wide variety of PLL circuits including modem devices.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a PLL circuit using the control method of the present invention, Fig. 2 is a block diagram of a PLL circuit using a conventional control method, Fig. 3 is an explanatory diagram of the operation of the PLL circuit, and Fig. 4 is a block diagram of a PLL circuit using a conventional control method.
．． FIG. 2 is a diagram showing a second control example. DESCRIPTION OF SYMBOLS 1... Phase comparator section, 1-1... Binary quantization phase comparator, 1-2... Multiplier, 2... Loop filter section, 2-1.2-4... Adder, 2-2... Delay circuit, 2-3... Multiplier, 3... Digital 700 part, 3
-1, 3-2...adder, 3-3...delay circuit,
3-4...Sine value generation circuit, 4...PLL input terminal. 9)) I-Gofil 7th m-----1 -1 - Mr. J Honhatsu Hyakutsuki Handicraft Wholesaler) A professional PLL idiom, 7 Figure 1 PLL idiom t-creation Crest U diagram Figure 3■ L--1-----------------1-11-''
-Yamamoto tlt Mr. Kanoriki Yoro PLL times 1 Tanicho pro, 7th figure 2nd +, K2's 1st party TT 4711 Fig.4

Claims (1)

[Claims] In a control method for a PLL circuit including a phase comparator section, a loop filter section, and a voltage controlled oscillator section, the value of the conversion gain coefficient of the phase comparator section is controlled from large to small according to the passage of time, and A control method for a PLL circuit, characterized in that a loop gain of a filter section is controlled from small to large in response to a change in the conversion gain coefficient.