JPH02211736A - Clock synchronizing circuit - Google Patents

Abstract

PURPOSE:To improve the follow-up characteristic and S/N by changing the noise band in accordance with the synchronous state. CONSTITUTION:At the time of synchronization, a current I scarcely flows to a resistance R1, and diodes X1 and X2 are turned off because an output voltage V2 of a loop filter is approximately equal to an input voltage V1, and the noise band of the loop filter 2 is narrowed. At the time of leading-in of synchronization, the input voltage V1 is greatly changed and the diode X1 or X2 is turned on, and thereby, the resistance R1 is switched to the resultant resistance of resistances R1 and R3 and the noise band of the loop filter is widened. Thus, the follow-up characteristic and S/N are improved together.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock synchronization circuit for a multi-value digital signal demodulator such as multi-value PSK or QAM, and in particular to a clock synchronization circuit for a multi-value digital signal demodulator such as a multi-value PSK or QAM
The present invention relates to a clock synchronous circuit having a phase lock loop (Phase Lock Loop).

(Conventional technology) A conventional clock synchronization circuit is shown in FIG.

In FIG. 2, 1 is a phase comparison circuit, 2' is a loop filter, and 3 is a voltage controlled oscillator (VCO).

The clock a extracted from the baseband signal (demodulated signal) of the multilevel PSK or QAM demodulator is input to one input terminal of the phase comparator l. The output of the VCO3 is input to the other input terminal of the phase comparator l. A signal (regenerated clock) d is input. When the frequency and phase of clock a change, an output voltage corresponding to the phase difference between the above-mentioned extracted clock a and the output signal d of the VCO 3 is output from the phase comparator 1, and the signal is passed through a loop filter (generally an RC filter) 2'. C is supplied to VCO3. This signal C controls the VCO 3 to match the phase of its output signal d with the phase of the clock a, thereby achieving clock synchronization.

[Problem to be solved by the invention]

In the conventional clock synchronization circuit described above, if the noise band of the loop filter 2' is wide, the tracking characteristic of the regenerated lock d with respect to the phase change of the clock a is good, but the signal-to-noise ratio of the regenerated clock ( S/
There is a problem that N) becomes worse. Furthermore, as multilevel modulation becomes more common, there is a problem in that, if the noise band of the loop filter 2' is set so as to follow clock frequency and phase fluctuations without problems, the S/N ratio of the reproduced clock will deteriorate more.

An object of the present invention is to provide a clock synchronization circuit that improves tracking characteristics or S/N by changing the noise band depending on the synchronization state.

[Means for Solving the Problems] A clock synchronization circuit of the present invention includes a phase comparator, a loop filter, and a pressure-controlled oscillator, and the loop filter in parentheses generates noise in the loop filter in response to the output of the phase comparator. It is equipped with a diode circuit that changes the band.

[Effect]

In the above-described configuration, the diode circuit turns on and off to change the RC value of the RC-configured filter and change its noise band.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a PLL of a clock synchronization circuit according to the present invention.

In FIG. 1, 1 is a phase comparator, 2 is a loop filter, and 3 is a vCO. Here, the loop filter 2 includes resistors R1 to R3, a capacitor C, and diodes XI, X
It is composed of 2. That is, the loop filter 2 is RC
Configured as a filter, resistors R1, R2, and capacitor C are connected as shown, parallel diodes XI and X2 with opposite connections to each other are connected in series with resistor 3, and this series circuit is connected in parallel with resistor R1. ing.

According to this configuration, when the frequency and phase of the clock change, the extracted clock a is input to the phase comparator 1, and its output signal passes through the loop filter 2 and controls the voltage controlled oscillator 3. Steady state (synchronized state or state close to this Li)
Since almost no current I flows through the resistor R, the output voltage (2) of the loop filter is approximately equal to the input voltage (1), so the diodes XI and X2 are turned off.

On the other hand, when the frequency and phase of the clock change greatly, such as when the demodulator is synchronized, the input voltage Vl changes greatly and diode XI (or X2) turns on, so that the resistor R1 is It becomes a composite resistance, and the noise band of the loop filter widens. In other words, by widening the noise band of the loop filter 2, the follow-up characteristic of the reproduced clock d with respect to the extracted clock a is improved, and clock synchronization is accelerated. Thereafter, when the phase difference between the extracted clock a and the reproduced clock d becomes smaller, v1ζ■2 again occurs, the diodes XI and X2 are turned off, and the noise band of the loop filter 2 becomes narrower.

〔Effect of the invention〕

As explained above, the present invention provides a loop filter with a diode circuit that turns on and off depending on the output voltage of the phase comparator of the PLL, thereby widening the noise band and improving the tracking characteristics in cases such as when locking. This has the effect of narrowing the noise band and improving the S/N ratio in cases such as a synchronous state.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a clock synchronous circuit of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional clock synchronous circuit. 1... Phase comparator, 2.2'... Loop filter,
3... Voltage controlled oscillator, XI, X2... Diode, R1 to R3... Resistor, C... Capacitor.

Claims (1)

[Claims] 1. A phase comparator that inputs a recovered clock and a clock extracted from a demodulated signal, a loop filter connected to the output of this phase comparator, and a voltage control that outputs the recovered clock in response to the output of this loop filter. A clock synchronous circuit comprising an oscillator, wherein the loop filter is provided with a diode circuit that changes the noise band of the loop filter in response to the output of the phase comparator.