JPH06505843A - Circuit that generates color subcarrier from color synchronization signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] A circuit for generating a color subcarrier from a color synchronization signal The present invention is described in the preamble of claim 1. Regarding the circuit. This type of PLL circuit essentially includes a phase comparator stage, a controlled oscillator, and and a filter element between the output of the phase comparison stage and the adjustment input of the oscillator.

The oscillator is preferably designed as a crystal oscillator. In this case, generally water The crystal can be used as an external component, e.g. an integrated circuit with a phase comparator stage and a controlled oscillator. (IC>), typically in terms of the component and crystal values. Adjustments are required due to variations in This adjustment is advantageous for crystals. This is done by an adjustable capacitor connected externally to the IC in parallel.

The object of the present invention is to provide a circuit that can be easily manufactured as an integrated circuit and that does not require adjustment of a controlled oscillator. According to the invention, this problem is solved by providing a phase comparator stage. The output side of the A/D converter is a digital PLL filter and a Cedamer delta- Connected to filter capacitor via digital/analog converter It is solved by

The digital output voltage of the A/D converter used for phase comparison is converted into an analog signal for the oscillator. There are a number of possible configurations and circuits per se for converting to a regulated voltage.

Here, the above-mentioned PLL filter and special A/A converter are assembled as in the present invention. By combining these functions, the lock-in range of the entire color subcarrier PLL can be significantly expanded. It turned out that. This lock-in range defines the components and especially the frequency. Even considering all the tolerances in the crystal used, the frequency tuning of the color subcarrier oscillator is It is so spacious that it is no longer necessary. This is especially true in the past when outside the IC. This means that the trimmer capacitor that was required to be installed in parallel with the crystal can be omitted. do.

This provides significant cost advantages.

This is due to the trimmer capacitor, which is an individual component, and the work cost for assembly. In addition, manual adjustment of this capacitor is omitted. Therefore Externally, the IC essentially consists of a crystal without a trimmer capacitor and an analog control. It only requires a filter capacitor to provide a rectified voltage. All other than these The circuit can be placed on a digital 0MO8-IC at significantly lower cost.

Advantageously, the digital PLL filter has a gate pulse on the active input side of the filter. It can be used additionally as a color synchronization signal gating stage by adding a advantageously The output voltage of the oscillator is applied to the clock input side of the D/A converter via the divider. It will be done. The output of the A/D converter is connected to the processor, and this processor Two digital color difference signals are supplied from the output side.

These two digital color difference signals are applied to the input side of the digital PLL filter. It will be done. Advantageously, the voltage values of the two supplied color difference signals corresponding to the color synchronization signal are By evaluating both components of 0 evaluated in the digital filter, the Improved PLL lock-in characteristics can be obtained.

Next, the invention will be explained based on one embodiment with reference to the drawings.

FIG. 1 is a block circuit diagram of an IC in which color subcarrier processing according to the present invention is performed. .

FIG. 2 is a block circuit diagram of an embodiment of a digital PLL filter.

FIG. 3 is a block diagram of an embodiment of a sigma-delta digital-to-analog converter. It is a circuit diagram.

In the case of Figure 1, a video signal containing a luminance signal and a modulated chrominance subcarrier is integrated It reaches the A/D converter 2 from the terminal l of the circuit 16. Clock input of A/D converter 2 The output side of the VCXO crystal oscillator 11 is connected to the side. This oscillator is A color subcarrier F4 having a frequency 4*Fsc that is four times the carrier frequency is generated.

A crystal 14 that determines the frequency of the oscillator 11 is externally connected to terminals 12 and 13. ing. The regulation of the oscillator 11 is determined by the analog regulation voltage U supplied via the line lO. This is done by R. The output signal of the A/D converter 2 reaches the processor 3. there The signal is demodulated at the output side 4.5, and the digital color difference signals R-Y and B are output to the output side 4.5. -Y occurs. These signals are fed to other circuit parts of the IC for further processing. It will be done. Furthermore, both of these signals also reach the input side of the digital PLL filter 6. , on the other hand, the color synchronization signal - gate pulse BGP (part In the filter 6, the gate pulse is supplied. Only voltage values corresponding to the color synchronization signal are evaluated. This is necessary. This is because the quadrature-modulated color subcarrier is modulated by the image content during the line sweep. This is because it is not suitable for synchronizing the oscillator 11. PLL fee The value calculated by the router 6 is converted to a sigma-delta digital/analog converter 8. supplied to Furthermore, a clock with a frequency of 2Fsc is connected to the clock input side of the converter 8. Lock T2 is added. This clock is passed through a frequency divider 15 with a division coefficient of 2. and is obtained from the color subcarrier F4. The output signal of converter 8 is a pulsed current iL. This current is connected to the color synchronization signal from terminal l and the color subcarrier F4 from the oscillator 11. Depending on the phase difference detected between the filter capacitor CF connected to the terminal P to charge or discharge. As a result, an analog regulation voltage UR is generated at terminal P, and this The regulated voltage reaches the regulated input of the oscillator 11 via line 10.

FIG. 2 shows a detailed block circuit diagram regarding the digital PLL filter 6. It is. During the duration of the color synchronization signal, inputs IBY and IRY have no color synchronization signal. demodulated color difference signals (B-Y) and (R-Y) corresponding to the respective component of the signal; is added. The gate pulse BGP supplied externally for the color synchronization signal is The period signal has its rising edge in the middle and occurs once for each scan line.

And registers RO and R1 output digital values IBM and IRY. hand over. The values previously present in registers RO and R1 are transferred to register R2. , is handed over to R3.

Adder AO combines the value actually received at IBM with the value from the previous scan line. Calculate the sum. The calculated value is only significant for the polarity sign bit BM. this The bits are on the control input side of register R4, exclusive OR gate GO1 and adder A3. reach. The actually calculated polarity sign bit BM and the preceding scan of the output side of R4 If the values of BM on the lines are equal, the output BE of inverter G4 becomes the logical value l. Ru. Otherwise, the output is a logic zero.

Adder AI converts the value actually received from input IRY to the value from the previous scan line. Add. This result is supplied to the limiter circuit Gl. This kind of limiter is advantageous can be realized by ROM. A positive number greater than -1 for the value 2** is this (12* *Replaced by k-1.

Similarly, numbers below the value 2** (-k) are replaced with this value 2** (-k). It will be done. All other values pass through the limiter unchanged. This way you get The added value RR reaches register R5 and adders A2 and A3.

Adder A2 adds the RR value in the previous scan line stored in register R5. Subtract from the actual RR value. Switch G2 can be realized as a multiple AND gate. Ru. This switch will pass the calculated value as is if it is BF-4, and if it is If not, the value 0 will appear on the output side. The output of switch G2 is multiplied by 2**N be done. This means that the binary value is shifted left by 8 places, and this left shift Technically, this is realized by shifting the lines in adder A3 and connecting them. Ru.

If BM has a negative polarity sign, adder A3 adds both input values. B If M is a positive polarity sign, digital signal R3 is subtracted from signal RR.

The result of adder A3 is supplied to limiter circuit G3.

After each rising edge of gate pulse BGP, a new value is sent as a digital electrical signal. passes through this entire circuit. After a predetermined time, the value at the input side of register R6 is in a stable state. become. This is achieved by the auxiliary clock BGH delayed from the gate pulse BGP. The result is stored in register R6 and can be retrieved at output DO. Shown in Figure 1 Do simultaneously converts the subsequent sigma-delta digital-to-analog converter 8 so that It is also an input.

FIG. 3 shows a detailed block diagram of the converter 8 connected to terminal Do. There is. The converter 8 is configured as a first order digital sigma-delta modulator. Ru. The input Do of the sigma-delta modulator is an n-bit wide digital path.

Numbers are expressed as two's complement numbers. In this case, n=4 is shown as an example. , so values between -8 and +7 can be added to the input side. 1st step As a step, polarity code addition Vo is executed. Adder AIO registers this value. It is added to the output value to which the polarity sign of R11 has been added. 4 of the lower value of adder AIO The two sum bits are fed to the input of register R11. Output S of adder AIO 3 and S4 are coupled together through gates Glo and Gll, and resistor R 12 and R13 at the outputs U and D.

Registers R11, R12, R13 are interrupted with a fixed frequency of approximately 8MHz. It is driven by a clock T2 that is not used. Digital voltages U and D are connected to switch S1 0 and Sll. Terminal P is connected to both switches and the oscillator connected to the high resistance control voltage input side OCv and the external filter capacitor CF. It is. Current sources I0 and 11 realized by transistors have equal nominal voltages. Provides flow value.

For example, if U=1 and D=O, the current of the current source IO will be at the indicated position "1" flows into filter capacitor CF via switch 310 at Increase the voltage UR at CF. From the positive supply voltage jiff(+), the current is At the "0" position, the current flows to the current source 1 via the switch Sll. Therefore In the case of a lever, this branch does not affect the voltage at capacitor CF. this In this way, the terminal P connected to the filter capacitor CF is connected to water according to FIG. An analog adjustment voltage UR for frequency and phase adjustment of the crystal oscillator 11 is generated.

This entire circuit, shown in Figure 1.2.3, is part of a digital CMO3-IC. This 0MO3-IC has additional features not shown in Figure 1. For zero-color subcarrier generation, which also includes other signal processing components, there are no external components of the IC. Crystal 14 and filter capacitor CFL are not required. Filtering by CF The time constant corresponds to approximately 200-300 television scan lines. capacitor CF performs an integral function together with the PI adjuster implemented within the converter 8. CF is It has a capacitance on the order of lμF. In this way, the first phase that performs the function of color subcarrier generation In the PLL circuit according to FIG. 1, an oscillator 11 forms a VCo and an A/D converter 2 forms a phase comparator stage, stage 6.8 and CF form a filter, by which An analog regulation voltage UR for the oscillator 11 is formed from the digital comparison result. .

Do international search report international search report

Claims (5)

[Claims] 1. A PLL circuit equipped with an A/D converter (2) is provided, and the A/D conversion (2) Hepideo signal and the output voltage of the VCXO crystal oscillator (11) as a clock. pressure is applied, and the output side of the A/D converter is connected to the oscillator ( 11) A filter capacitor (CF ), in a circuit that generates a color subcarrier from a color synchronization signal, The output side of the A/D converter is a digital PLL filter (6) and a sigmar del filter capacitor (CF) through the digital/analog converter (8) A circuit for generating a color subcarrier from a color synchronization signal, characterized in that: 2. Said PLL filter (6) additionally has a gate pass on the enable input (7). (BGP) can be used as a color synchronization signal gate stage. The circuit according to item 1. 3. The output voltage of the oscillator (11) is passed through a frequency divider (15) to a D/A converter ( 8). The circuit according to claim 1, being applied to the clock input side of 8). 4. The output side of the A/D converter (2) is connected to the processor (3), and the output side of the A/D converter (2) is connected to the processor (3). The processor sends out two digital color difference signals (R-Y, B-Y) from the output side. , the color difference signal is applied to the input side of the digital PLL filter (6). The circuit according to claim 1. 5. Both supplied digital color difference signals (R-Y, B- The voltage value of Y) is evaluated in the digital PLL filter (6). The circuit according to item 4.