JPH0272699A - Method for soldering lead electrode and lead wire in hybrid integrated circuit - Google Patents
Method for soldering lead electrode and lead wire in hybrid integrated circuitInfo
- Publication number
- JPH0272699A JPH0272699A JP63224253A JP22425388A JPH0272699A JP H0272699 A JPH0272699 A JP H0272699A JP 63224253 A JP63224253 A JP 63224253A JP 22425388 A JP22425388 A JP 22425388A JP H0272699 A JPH0272699 A JP H0272699A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- solder
- integrated circuit
- hybrid integrated
- lead electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 11
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 title abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000006071 cream Substances 0.000 abstract description 7
- 238000012937 correction Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000779 smoke Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、混成集積回路におけるリード電極とリード線
の半田付は方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for soldering lead electrodes and lead wires in a hybrid integrated circuit.
（従来の技術） 混成集積回路は、次のような工程によって製造される。(Conventional technology) Hybrid integrated circuits are manufactured through the following steps.
■ アルミナ基板を洗浄した後、該アルミナ基板上にパ
ターン印刷を施し、乾燥、焼成する。(2) After cleaning the alumina substrate, a pattern is printed on the alumina substrate, dried and fired.
■ 抵抗を印刷し、乾燥、焼成した後、抵抗トリミング
を行なう。■ After printing, drying and firing the resistor, perform resistor trimming.
■ レジスト印刷し、乾燥させる。■ Print the resist and let it dry.
■ メタルマスクによりクリームはんたを電極に印刷す
る。■ Print cream solder on the electrodes using a metal mask.
■ 該クリーム半田塗布部上にチップ部品をマウントす
る。■ Mount the chip component on the cream solder application area.
■ リフロー炉によりチップ部品と電極とを半田付けす
る。■ Solder the chip parts and electrodes using a reflow oven.
■ ファンクショナルトリミングを行なう。■ Perform functional trimming.
■ 混成集積回路基板を分割する。■ Divide the hybrid integrated circuit board.
■ リードフレームのリード線の先端を、分割された混
成集積回路基板のリード電極に接触させながら半田付け
を行なう。■ Solder while bringing the ends of the lead wires of the lead frame into contact with the lead electrodes of the divided hybrid integrated circuit board.
［相］ フラックス洗浄をする。[Phase] Perform flux cleaning.
混成集積回路基板ａには、半導体チップ・厚膜抵抗等加
熱されると特性か変化したり、損傷したりしてしまう電
子部品が実装されているため、前記■工程におけるフレ
ームリードの半田付けは、第５図示のように、リード電
極部分を局部的に加熱させ、米軍ｎｌ ｅを供給させな
がら、リードフレームＣのリード線ｄを半田付けしてい
る。The hybrid integrated circuit board a is mounted with electronic components such as semiconductor chips and thick film resistors that change their characteristics or are damaged when heated, so the soldering of the frame leads in the above step 2 is not necessary. As shown in Figure 5, the lead wires d of the lead frame C are soldered while locally heating the lead electrode portion and supplying US military nle.
すなわち、まずコンデンサ、半導体チップ等の電子部品
か搭載された（図示せず）混成集積回路基板ａのリード
電極す上に第６図示のようにフレームリードＣのリード
線ｄの先端を載せる。次に、フラックス入り米軍［１１
ｅを送りローラｆによって半田送りパイプｇから半田付
は部に供給し、その糸半田ｅの先端近傍に設けられたバ
ーナｈで糸半田ｅの先端近傍を加熱して糸半田ｅを溶融
する半田付は装置ｉに、ベルトｊを移動させて分割され
た混成集積回路基板ａ及びリードフレームＣを近づける
。これ等が半田付は装置ｌに近づくと、送り一ローラｆ
が回転して糸半田ｅが供給され、その先端部がバーナｋ
ｌによって加熱され、リードフレームＣのリード線ｄが
混成集積回路基板ａのリード電極すに第７図示のように
半田（ｋ）付けされる。That is, first, as shown in the sixth figure, the tips of the lead wires d of the frame leads C are placed on the lead electrodes of a hybrid integrated circuit board a (not shown) on which electronic components such as capacitors and semiconductor chips are mounted. Next, the flux-cored US military [11
Solder e is supplied to the soldering part from a solder feed pipe g by a feed roller f, and the vicinity of the tip of the thread solder e is heated by a burner h provided near the tip of the thread solder e to melt the thread solder e. Next, the divided hybrid integrated circuit board a and the lead frame C are brought closer to the apparatus i by moving the belt j. When these are soldered, as they approach the device l, feed roller f
rotates to supply the thread solder e, and its tip is connected to the burner k.
1, and the lead wires d of the lead frame C are soldered (k) to the lead electrodes of the hybrid integrated circuit board a as shown in FIG.
（発明が解決しようとする課題）
上記した従来の半ＦＤ付は方法によれば、フラックス入
り糸半田ｅをバーナｈによって加熱するとフラックスの
煙りが発生し、この煙りによって半田送りパイプｇが詰
まってしまい、１［常に糸半田ｅを供給することができ
にくくなるために、メインテナンスを必要とした。(Problems to be Solved by the Invention) According to the above-described conventional semi-FD attachment method, when the flux-cored solder wire e is heated by the burner h, flux smoke is generated, and the solder feed pipe g is clogged by this smoke. 1) Maintenance was required because it became difficult to constantly supply thread solder e.
また糸半田ｅを用いているために供給にばらつきが生じ
、半田被石部の位置か一定にならず、そのため修正しな
ければならなかった。Furthermore, since the thread solder e was used, there were variations in the supply, and the position of the solder stone part was not constant, so correction had to be made.
本発明は、以上の従来方法の課題を解決することをその
目的とするものである。An object of the present invention is to solve the problems of the conventional methods described above.
（課題を解決するための手段）
本発明は、上記の目的を達成するために、混成集積回路
基板の端縁に添って設けられたリード電極上に予め半田
を被むさせておき、その上にリード線を載せ、該半田部
分を局部的に加熱し溶融させて前記リード電極にリード
線を半田付けすることを特徴とする。前記半田被着面積
は前記リード電極より広くすることが好ましい。(Means for Solving the Problems) In order to achieve the above object, the present invention covers lead electrodes provided along the edges of a hybrid integrated circuit board in advance with solder, and The method is characterized in that a lead wire is placed on the electrode, and the solder portion is locally heated and melted to solder the lead wire to the lead electrode. Preferably, the solder application area is larger than the lead electrode.
（作 用）
例えば、混成集積回路の前記製造工程■の段階でリード
電極上にクリーム半田を印刷して混成集積回路基板のリ
ード電極上に予め半田を被着させておく。リード線をリ
ード電極に半田付けするときは、該リード電極上にリー
ド線を載せ、例えばバーナで半田を加熱して溶融し、リ
ード線をリード電極に半田付けする。リード電極上の半
田被着面積をリード電極より広くすると、溶融半田はリ
ード線の全周面を覆うためにリード線とリード電極との
間の半田付は強度が強くなる。(Function) For example, in step (2) of the hybrid integrated circuit manufacturing process, cream solder is printed on the lead electrodes to coat the lead electrodes of the hybrid integrated circuit board in advance. When soldering a lead wire to a lead electrode, the lead wire is placed on the lead electrode, the solder is heated and melted using, for example, a burner, and the lead wire is soldered to the lead electrode. When the solder area on the lead electrode is made larger than that of the lead electrode, the solder strength between the lead wire and the lead electrode becomes stronger because the molten solder covers the entire circumferential surface of the lead wire.
（実施例） 以下本発明の実施例を図面につき説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
アルミナ基板上にパターン印刷を施し、次いで抵抗を印
刷し、該抵抗のトリミングを行ない、レジスト印刷を施
し、メタルマスクにより電極にクリーム半田を印刷した
。このときリード電極上にもクリーム半田を印刷した。A pattern was printed on the alumina substrate, then a resistor was printed, the resistor was trimmed, resist printing was performed, and cream solder was printed on the electrodes using a metal mask. At this time, cream solder was also printed on the lead electrodes.
その後、チップ部品をアルミナ基板のクリーム半［ｌ塗
付部にマウントし、リフロー炉によりチップ部品と電極
とを半田付けした。その時のアルミナ基板１のリード電
極２には、第１図示のように、半田３が被着されている
。Thereafter, the chip component was mounted on the cream semi-coated area of the alumina substrate, and the chip component and the electrode were soldered in a reflow oven. At this time, the lead electrodes 2 of the alumina substrate 1 are coated with solder 3, as shown in the first figure.
このような基板のリード電極上にリード線の先端部を載
せ、バーナにより加熱して第２図示のように、リード電
極２にリード線４を半田（３）付けした。The tip of the lead wire was placed on the lead electrode of such a substrate, heated with a burner, and the lead wire 4 was soldered (3) to the lead electrode 2 as shown in the second figure.
従来の半田付は方法によると、半田被着部の位置の修正
を必要としたものは、５％〜６％であったのが、この実
施例によれば０％であった。According to conventional soldering methods, 5% to 6% of cases required modification of the position of the solder-applying portion, but according to this embodiment, it was 0%.
半田３の被着面積を第３図示のようにリード電極２の面
積より約３０％広くしたとき、該リード電極２に半田付
けしたリード線４の全周面は第４図示のように半田３で
覆われ、半■１付は強度が強くなった。When the area to which the solder 3 is applied is made approximately 30% larger than the area of the lead electrode 2 as shown in the third figure, the entire circumferential surface of the lead wire 4 soldered to the lead electrode 2 is covered with the solder 3 as shown in the fourth figure. The strength of the half-■1 has become stronger.
（発明の効果）
本発明は、上述のように構成されているので、糸半田汚
れが生しないと共に、半１１被着位置にばらつきがなく
なるため位置修正を必要としない。また、無駄な半ＩＴ
Ｉがなくなるために半田使用量が低減する。更に混成集
積回路の製造の過程でリード電極への半田付は作業を行
なうことができ、リード電極とリード線の半田付は作業
か容すかつ迅速に行なうことができる効果を有する。(Effects of the Invention) Since the present invention is configured as described above, no solder thread stains occur, and there is no need for position correction because there is no variation in the position of the half 11 attached. Also, useless semi-IT
Since I is eliminated, the amount of solder used is reduced. Furthermore, the soldering to the lead electrodes can be carried out in the process of manufacturing a hybrid integrated circuit, and the soldering of the lead electrodes and the lead wires can be carried out easily and quickly.
第１図及び第２図は、本発明方法により、リード電極に
予め半田を被着させた状態及び該半田を溶融してリード
電極とリード線とを半田付けした状態をそれぞれ示す断
面図、第３図及び第４図は半田被着面積を広くした場合
の第１図及び第２図に対応する断面図、第５図は従来の
半田付は方法の説明図、第６図及び第７図は、第５図示
の方法によりリード線をリード電極に半１−１１付けす
る前と後の状態を示す平面図である。
１・・・アルミナ基板
２・・・リード電極
３・・・半 田
４・・・リード線
許
出
理
願
太陽誘電株式会社
北 村 欣
外３名1 and 2 are cross-sectional views showing a state in which the lead electrode is preliminarily coated with solder and a state in which the lead electrode and the lead wire are soldered by melting the solder, respectively, according to the method of the present invention. Figures 3 and 4 are cross-sectional views corresponding to Figures 1 and 2 when the solder adhesion area is increased, Figure 5 is an explanatory diagram of the conventional soldering method, and Figures 6 and 7. FIG. 5 is a plan view showing the state before and after the lead wire is attached to the lead electrode in half 1-11 by the method shown in FIG. 1...Alumina substrate 2...Lead electrode 3...Solder 4...Lead wire permission application Taiyo Yuden Co., Ltd. Kingai Kitamura 3 people
Claims (2)
電極上に予め半田を被着させておき、その上にリード線
を載せ、該半田部分を局部的に加熱し溶融させて前記リ
ード電極にリード線を半田付けすることを特徴とする混
成集積回路におけるリード電極とリード線の半田付け方
法。1. Solder is applied in advance to the lead electrodes provided along the edges of the hybrid integrated circuit board, the lead wires are placed on top of the solder, and the solder portions are locally heated to melt and attach to the lead electrodes. A method for soldering lead electrodes and lead wires in a hybrid integrated circuit characterized by soldering lead wires.
とを特徴とする請求項１記載の混成集積回路におけるリ
ード電極とリード線の半田付け方法。2. 2. The method of soldering lead electrodes and lead wires in a hybrid integrated circuit according to claim 1, wherein the solder adhesion area is made larger than the lead electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63224253A JPH0272699A (en) | 1988-09-07 | 1988-09-07 | Method for soldering lead electrode and lead wire in hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63224253A JPH0272699A (en) | 1988-09-07 | 1988-09-07 | Method for soldering lead electrode and lead wire in hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0272699A true JPH0272699A (en) | 1990-03-12 |
Family
ID=16810882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63224253A Pending JPH0272699A (en) | 1988-09-07 | 1988-09-07 | Method for soldering lead electrode and lead wire in hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0272699A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011209422A (en) * | 2010-03-29 | 2011-10-20 | Fujikura Ltd | Method for manufacturing optical module |
| US8777498B2 (en) | 2010-06-03 | 2014-07-15 | Fujikura Ltd. | Method for manufacturing optical module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01169885A (en) * | 1987-12-25 | 1989-07-05 | Optec Dai Ichi Denko Co Ltd | Soldering method |
| JPH01171294A (en) * | 1987-12-25 | 1989-07-06 | Nec Kansai Ltd | Soldering method |
-
1988
- 1988-09-07 JP JP63224253A patent/JPH0272699A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01169885A (en) * | 1987-12-25 | 1989-07-05 | Optec Dai Ichi Denko Co Ltd | Soldering method |
| JPH01171294A (en) * | 1987-12-25 | 1989-07-06 | Nec Kansai Ltd | Soldering method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011209422A (en) * | 2010-03-29 | 2011-10-20 | Fujikura Ltd | Method for manufacturing optical module |
| US8777498B2 (en) | 2010-06-03 | 2014-07-15 | Fujikura Ltd. | Method for manufacturing optical module |
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