JPH06177514A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH06177514A JPH06177514A JP34362392A JP34362392A JPH06177514A JP H06177514 A JPH06177514 A JP H06177514A JP 34362392 A JP34362392 A JP 34362392A JP 34362392 A JP34362392 A JP 34362392A JP H06177514 A JPH06177514 A JP H06177514A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- temperature
- plating layer
- pad
- plated layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、表面実装部品をはんだ
付けするパッドに、はんだめっきによりはんだを供給し
たプリント配線板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board in which solder is supplied by solder plating to pads for soldering surface mount components.
【０００２】[0002]
【従来の技術】チップ部品などの表面実装部品をパッド
にはんだ付けする際に、はんだの付きを良くするために
パッドに予め十分な量のはんだを供給しておく必要があ
る。2. Description of the Related Art When soldering a surface mount component such as a chip component to a pad, it is necessary to supply a sufficient amount of solder to the pad in advance in order to improve the soldering property.
【０００３】パッドにはんだを予め供給する方法とし
て、パッドに銅めっきあるいは薄くはんだコーティング
した後、はんだペースト（クリームはんだ）を印刷によ
り塗布し加熱溶融させる方法が公知である。As a method of supplying solder to the pad in advance, there is known a method of applying copper plating or thin solder coating to the pad, then applying a solder paste (cream solder) by printing and heating and melting.
【０００４】一方回路パターンのリード間隔（あるいは
パッドの間隔）が０．３mmというように特に細かいパタ
ーンの場合には、それぞれのリード（パッド）にはんだ
ペーストを塗布するのが困難である。そこでこの場合に
は基板表面のリード（パッド）以外の部分を含めて全面
に均一にはんだペーストを塗布し、加熱することによ
り、表面張力で回路パターン以外の部分の溶融はんだを
回路パターン上に引き寄せる方法が従来より使われてい
る。On the other hand, when the lead interval (or pad interval) of the circuit pattern is a particularly fine pattern such as 0.3 mm, it is difficult to apply the solder paste to each lead (pad). Therefore, in this case, the solder paste is uniformly applied to the entire surface including the parts other than the leads (pads) on the substrate surface and heated to draw the molten solder in the parts other than the circuit pattern onto the circuit pattern by surface tension. The method is traditionally used.
【０００５】またはんだめっきにより十分に厚いはんだ
めっき層を析出させる方法も公知である。図２はこの方
法の手順を説明する図である。この図の（Ａ）において
１は基材の樹脂層、２はこの樹脂層１に張り付けられた
銅箔である。この銅箔２には回路パターン部分を残して
パターン銅めっきレジスト３が印刷される。そしてパタ
ーン銅めっき層４がめっきされ、さらにその上にはんだ
めっき層５が厚く形成される。A method of depositing a sufficiently thick solder plating layer by dull plating is also known. FIG. 2 is a diagram for explaining the procedure of this method. In FIG. 1A, 1 is a resin layer of a base material, and 2 is a copper foil attached to the resin layer 1. A pattern copper plating resist 3 is printed on the copper foil 2 leaving a circuit pattern portion. Then, the patterned copper plating layer 4 is plated, and the solder plating layer 5 is thickly formed thereon.
【０００６】次に同図（Ｂ）のようにレジスト３が除去
される。そしてエッチングにより銅箔２を除去すると、
（Ｃ）のようにはんだめっき層５で覆われた回路パター
ンが形成される。Next, the resist 3 is removed as shown in FIG. When the copper foil 2 is removed by etching,
As shown in (C), a circuit pattern covered with the solder plating layer 5 is formed.
【０００７】この厚いはんだめっき層５を析出させる方
法では、めっき表面が無数の微細孔を有する粗面とな
る。このため酸化し易く、不純物が侵入し易くなり、は
んだ付けの信頼性低下を招く。例えば大気中の水分や空
気が僅かに溶け込むと、はんだ付け部にボイドやピンホ
ールなどの欠陥を発生させ易くなる。また不純物の侵入
ははんだのぬれ性や流動性を害し、はんだ付け部の耐腐
蝕性を低下させる重大な原因ともなる。In the method of depositing the thick solder plating layer 5, the plating surface becomes a rough surface having innumerable fine holes. For this reason, it is easy to oxidize, impurities are likely to enter, and the reliability of soldering is reduced. For example, when moisture or air in the atmosphere is slightly dissolved, defects such as voids and pinholes are easily generated in the soldered portion. Further, the invasion of impurities impairs the wettability and fluidity of the solder and becomes a serious cause of lowering the corrosion resistance of the soldered portion.
【０００８】そこで厚いはんだめっき層を析出させた
後、このめっき層を加熱溶融処理（フュージング）す
る。図２の（Ｄ）はこの処理後の状態を示すものであ
る。この図で５Ａははんだめっき層５が溶融した後凝固
したものを示す。Then, after depositing a thick solder plating layer, this plating layer is heated and fused (fusing). FIG. 2D shows the state after this processing. In this figure, 5A indicates that the solder plating layer 5 is melted and then solidified.
【０００９】[0009]
【従来技術の問題点】はんだペーストを印刷により塗布
する方法では、十分なはんだ量をパッドに供給するため
にははんだペーストの供給量を増やす必要がある。しか
しこの場合には回路パターン間にはんだが流れ、はんだ
のブリッジが発生し易いという問題が生じる。In the method of applying solder paste by printing, it is necessary to increase the supply amount of solder paste in order to supply a sufficient amount of solder to the pad. However, in this case, there arises a problem that solder flows between the circuit patterns and a solder bridge easily occurs.
【００１０】基板の表面全面にはんだペーストを塗って
表面張力を利用して回路パターン上にはんだを集める方
法では、はんだの量（はんだペーストに含まれるはんだ
粒子の量）を増やすと回路パターン間にやはりブリッジ
が発生し易いという問題がある。In the method of applying the solder paste on the entire surface of the substrate and collecting the solder on the circuit pattern by utilizing the surface tension, when the amount of solder (the amount of solder particles contained in the solder paste) is increased, the space between the circuit patterns is increased. After all, there is a problem that a bridge is likely to occur.
【００１１】また図２のように、厚いはんだめっき層５
を形成し、フュージング処理した場合には、図２（Ｄ）
に示すように溶融はんだの表面張力により回路パターン
すなわちパッド４の上面がかまぼこ状に盛り上がった曲
面となる。このような曲面になると、部品をパッド４に
押し付けて固定する場合に部品が不安定になる。すなわ
ちリフロー法では部品の電極をクリームはんだを排除し
つつパッドに押し付けて接着し、また浸漬法では部品の
電極をパッドに押付けた状態で接着剤により基板に接着
するからである。Further, as shown in FIG. 2, a thick solder plating layer 5 is formed.
Is formed and subjected to the fusing treatment, FIG.
As shown in FIG. 4, the surface tension of the molten solder causes the circuit pattern, that is, the upper surface of the pad 4 to be a curved surface that rises like a kamaboko. With such a curved surface, the component becomes unstable when the component is pressed against the pad 4 and fixed. That is, in the reflow method, the electrode of the component is pressed and bonded to the pad while removing the cream solder, and in the dipping method, the electrode of the component is pressed to the pad and bonded to the substrate with an adhesive.
【００１２】[0012]
【発明の目的】本発明は特にはんだめっき層を厚く形成
する場合に、部品の実装に適するようにはんだめっき層
の表面を平坦にすると共に、その表面の酸化や不純物の
侵入を防いではんだ付け性を低下させるおそれもなくな
るようにしたプリント配線板の製造方法を提供すること
を目的とする。It is an object of the present invention to make the surface of the solder plating layer flat so as to be suitable for mounting components, especially when forming a thick solder plating layer, and to prevent oxidation of the surface and invasion of impurities and soldering. It is an object of the present invention to provide a method for manufacturing a printed wiring board in which there is no possibility of reducing the property.
【００１３】[0013]
【発明の構成】本発明によればこの目的は、少くとも表
面実装部品をはんだ付けするためのパッドにはんだめっ
きを施し、基板をこのはんだめっき層のはんだ溶融温度
あるいはこの溶融温度より僅かに低い温度に加熱し前記
はんだめっき層を溶融させることなく所定時間保持した
後冷却することを特徴とするプリント配線板の製造方法
により達成される。SUMMARY OF THE INVENTION According to the invention, this object is to at least solder-pad the pads for soldering surface-mounted components and to solder the substrate to the solder melting temperature of this solder-plated layer or slightly below this melting temperature. This is achieved by a method for manufacturing a printed wiring board, which comprises heating to a temperature, holding the solder plating layer for a predetermined time without melting it, and then cooling the printed wiring board.
【００１４】ここにはんだめっき層の表面をはんだの溶
融温度より約３℃低い温度に約１５秒保持した後、自然
冷却するのが望ましい。It is desirable that the surface of the solder plating layer is kept at a temperature lower than the melting temperature of the solder by about 3 ° C. for about 15 seconds and then naturally cooled.
【００１５】[0015]
【実施例】図１は本発明の工程図である。この工程は図
２に示した従来方法に対して（Ｄ）のフュージング処理
工程が異なるのみである。すなわち図２（Ａ）のよう
に、レジスト３を印刷し（ステップ１００）、パターン
（パッド）４を銅めっきし（ステップ１０２）、このパ
ターン（パッド）４の上にはんだめっき層５を厚く析出
させる（ステップ１０４）。そしてレジスト３を除去し
た後（図２の（Ｂ）、ステップ１０６）、エッチングに
より不用な銅箔２を除去する（図２の（Ｃ）、ステップ
１０８）。FIG. 1 is a process chart of the present invention. This step is different from the conventional method shown in FIG. 2 only in the fusing treatment step (D). That is, as shown in FIG. 2A, the resist 3 is printed (step 100), the pattern (pad) 4 is copper-plated (step 102), and the solder plating layer 5 is thickly deposited on the pattern (pad) 4. (Step 104). After removing the resist 3 (FIG. 2B, step 106), the unnecessary copper foil 2 is removed by etching (FIG. 2C, step 108).
【００１６】このようにしてパターン（パッド）４には
んだめっき層５を厚く形成した後、このはんだめっき層
５のはんだの溶融温度より僅かに低い温度の液体に入
れ、所定時間加熱する（ステップ１１０）。例えば次の
ような条件で加熱処理し、自然冷却する。After thickly forming the solder plating layer 5 on the pattern (pad) 4 in this manner, the solder plating layer 5 is placed in a liquid having a temperature slightly lower than the melting temperature of the solder of the solder plating layer 5 and heated for a predetermined time (step 110). ). For example, heat treatment is performed under the following conditions and natural cooling is performed.
【００１７】[0017]
【表１】 はんだめっき厚さ １５μｍ はんだの組成 錫６０％、鉛４０％ 加熱温度 １８０℃ 加熱時間 １５秒[Table 1] Solder plating thickness 15 μm Solder composition 60% tin, 40% lead Heating temperature 180 ° C Heating time 15 seconds
【００１８】ここに析出した錫６０％・鉛４０％の組成
を持つはんだの融点は１８３℃であるから、この融点よ
りも３℃低い温度で加熱したものである。このように加
熱温度ははんだの融点よりも低いから、はんだめっき層
５は全く溶融することなく、その表面からある程度の深
さに達するまでの組織構造が変化し、その表面の微細孔
が消滅する。約１５秒間この液体に入れて加熱した後、
外へ出して室内（約２５℃±３℃）で自然冷却する。Since the melting point of the solder having a composition of 60% tin and 40% lead deposited here is 183 ° C., it is heated at a temperature 3 ° C. lower than this melting point. Since the heating temperature is lower than the melting point of the solder in this way, the solder plating layer 5 does not melt at all, the structure of the surface changes to reach a certain depth, and the micropores on the surface disappear. . Put in this liquid and heat for about 15 seconds,
Let it go out and cool it indoors (about 25 ℃ ± 3 ℃).
【００１９】このようにはんだめっき層５の表面を溶融
温度Ｔm 以下に加熱する場合には、はんだめっき層５は
全く溶融しない。しかしその合金の組織に変化が生じ
る。この状態変化の過程は通常のはんだ合金とは異なる
ものと考えられる。すなわち通常のはんだ合金によれば
公知の平衡状態図に基づいて説明ができるが、はんだめ
っき層５の場合には同じ平衡状態図を使って説明できる
か否か不明であるからである。In this way, when the surface of the solder plating layer 5 is heated to the melting temperature T m or lower, the solder plating layer 5 does not melt at all. However, changes occur in the structure of the alloy. The process of this state change is considered to be different from that of a normal solder alloy. That is, it can be explained based on a well-known equilibrium diagram according to a normal solder alloy, but it is unclear whether or not it can be explained using the same equilibrium diagram in the case of the solder plating layer 5.
【００２０】またこの処理後のはんだめっき層を湿度８
５％、温度８０℃の雰囲気に１週間放置して耐湿性試験
を行った。その結果未処理のものにはウィスカーの発生
が著しく、回路パターン間のショートやはんだ付け性の
低下が確認された。また熱処理を行ったものにはこのよ
うな変化は認められなかった。Further, the solder plating layer after this treatment has a humidity of 8
A humidity resistance test was conducted by leaving it in an atmosphere of 5% and a temperature of 80 ° C. for 1 week. As a result, whiskers were remarkably generated in the untreated product, and it was confirmed that a short circuit between circuit patterns and deterioration of solderability were caused. No such change was observed in the heat-treated product.
【００２１】液体で加熱する温度は、はんだめっき層５
の表面がこのはんだめっき層５のはんだ溶融温度を越え
ない範囲とするのが望ましい。しかしはんだめっき層５
の表面がはんだ溶融温度になっても、加熱時間が短けれ
ばはんだめっき層５の表面が僅かに溶融するだけである
から、はんだめっき層５の表面は平坦に保たれる。すな
わちはんだめっき層５の全体が流動して図２の（Ｄ）に
示すように流下して表面が曲面になることはない。本発
明はこのような方法も包含する。The temperature for heating with the liquid is the solder plating layer 5
It is desirable that the surface of the solder be within a range not exceeding the solder melting temperature of the solder plating layer 5. However, the solder plating layer 5
The surface of the solder plating layer 5 is kept flat because the surface of the solder plating layer 5 melts only slightly if the heating time is short even if the surface of the solder plating temperature becomes the solder melting temperature. That is, the entire solder plating layer 5 does not flow and flow down as shown in FIG. The present invention also includes such a method.
【００２２】一般には、はんだめっき層５の表面温度Ｔ
が、はんだ溶融温度Ｔm より５℃低い温度までの範囲、
すなわちＴm ＞Ｔ＞Ｔm −５℃、に設定するのが望まし
い。この場合には保持時間は１５〜２０秒位に設定する
のが望ましい。なお表面温度ＴはＴm −１０℃迄下げて
も本発明の効果を得ることは可能であり、この場合には
保持時間を２０秒以上に長く設定する。ここにはんだめ
っき層５の溶融温度Ｔm は、はんだの組成により変化す
る。一般に錫５５〜７０％、残鉛の組成を持つはんだで
は、その溶融温度を越えない範囲で１７５〜１８５℃に
加熱し、１５〜２０秒保持するのがよい。Generally, the surface temperature T of the solder plating layer 5 is
In the range up to 5 ° C. lower than the solder melting temperature T m ,
That is, it is desirable to set T m >T> T m −5 ° C. In this case, it is desirable to set the holding time to about 15 to 20 seconds. The effect of the present invention can be obtained even if the surface temperature T is lowered to Tm- 10 ° C. In this case, the holding time is set longer than 20 seconds. Here, the melting temperature T m of the solder plating layer 5 changes depending on the composition of the solder. Generally, for a solder having a composition of 55 to 70% tin and residual lead, it is preferable to heat the solder to 175 to 185 ° C. within a range not exceeding its melting temperature and hold for 15 to 20 seconds.
【００２３】[0023]
【発明の効果】請求項１の発明は以上のように、パッド
にはんだめっき層を厚く析出させた後、このはんだめっ
き層の表面温度がこのはんだの溶融温度あるいはこの溶
融温度より僅かに低い温度に加熱し、はんだめっき層の
全体を溶融させることなく所定時間保持し、その後冷却
するものであるから、はんだめっき層がパット上で流動
してその表面が丸くなることがない。As described above, according to the invention of claim 1, after the solder plating layer is thickly deposited on the pad, the surface temperature of the solder plating layer is the melting temperature of the solder or a temperature slightly lower than the melting temperature. Since the whole of the solder plating layer is heated for a predetermined time without being melted and then cooled, the solder plating layer does not flow on the pad and its surface is not rounded.
【００２４】このためはんだめっき層表面が平坦に保た
れ、表面実装部品を安定して保持しはんだ付けすること
が可能になる。またはんだめっき層の表面の微細孔が消
滅し、表面の酸化や不純物の侵入を防止でき、はんだ付
け性の低下を防ぐことができる。Therefore, the surface of the solder plating layer is kept flat, and the surface mount component can be stably held and soldered. In addition, the fine pores on the surface of the solder plating layer disappear, oxidation of the surface and intrusion of impurities can be prevented, and deterioration of solderability can be prevented.
【００２５】ここに加熱温度ははんだめっき層の表面温
度がこのはんだの溶融温度より約５℃低く、さらに好ま
しくは約３℃低くなるように設定し、この温度に約１５
秒間保持してから、自然冷却するのが望ましい（請求項
２）。The heating temperature is set so that the surface temperature of the solder plating layer is lower than the melting temperature of the solder by about 5 ° C., more preferably about 3 ° C., and the temperature is about 15 ° C.
It is desirable to hold for a second and then cool naturally (Claim 2).
【図１】本発明の処理工程の説明図FIG. 1 is an explanatory view of a processing step of the present invention.
【図２】従来の処理工程の説明図FIG. 2 is an explanatory view of a conventional processing step.
１ 基板 ２ 銅箔 ４ 回路パターン ５ はんだめっき層 1 substrate 2 copper foil 4 circuit pattern 5 solder plating layer
Claims (2)
ためのパッドにはんだめっきを施し、このはんだめっき
層をはんだ溶融温度あるいはこの溶融温度より僅かに低
い温度に加熱し前記はんだめっき層を溶融させることな
く所定時間保持した後冷却することを特徴とするプリン
ト配線板の製造方法。1. A pad for soldering at least a surface mount component is solder-plated, and this solder-plated layer is heated to a solder melting temperature or a temperature slightly lower than this melting temperature to melt the solder-plated layer. A method for manufacturing a printed wiring board, which comprises holding for a predetermined time without cooling and then cooling.
温度より約３℃低い温度に約１５秒間保持した後、自然
冷却する請求項１のプリント配線板の製造方法。2. The method for producing a printed wiring board according to claim 1, wherein the surface temperature of the solder plating layer is kept at a temperature about 3 ° C. lower than the solder melting temperature for about 15 seconds, and then naturally cooled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34362392A JPH06177514A (en) | 1992-12-01 | 1992-12-01 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34362392A JPH06177514A (en) | 1992-12-01 | 1992-12-01 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06177514A true JPH06177514A (en) | 1994-06-24 |
Family
ID=18362962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34362392A Pending JPH06177514A (en) | 1992-12-01 | 1992-12-01 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06177514A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7546681B2 (en) | 1999-10-12 | 2009-06-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| US9365947B2 (en) | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
-
1992
- 1992-12-01 JP JP34362392A patent/JPH06177514A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7546681B2 (en) | 1999-10-12 | 2009-06-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| US7721422B2 (en) | 1999-10-12 | 2010-05-25 | Tessera Interconnect Materials, Inc. | Methods of making microelectronic assemblies |
| US9365947B2 (en) | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
| US10283484B2 (en) | 2013-10-04 | 2019-05-07 | Invensas Corporation | Low cost substrates |
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