JPH0272075U - - Google Patents
Info
- Publication number
- JPH0272075U JPH0272075U JP15077788U JP15077788U JPH0272075U JP H0272075 U JPH0272075 U JP H0272075U JP 15077788 U JP15077788 U JP 15077788U JP 15077788 U JP15077788 U JP 15077788U JP H0272075 U JPH0272075 U JP H0272075U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- emitter
- switching transistor
- outputs
- blanking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Description
第1図は本考案に係る帰線消去回路の一実施例
を示す回路図、第2図は本考案の他の実施例を示
す回路図、第3図は従来の帰線消去回路を示す回
路図、第4図は第3図の動作を説明するためのタ
イミングチヤートである。
1……出力端子、Q3……トランジスタ、Q6
……エミツタホロワトランジスタ、R7,R8,
R14……抵抗、C3,C4……コンデンサ、D
Z……ツエナーダイオード。
FIG. 1 is a circuit diagram showing one embodiment of the blanking circuit according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional blanking circuit. 4 are timing charts for explaining the operation of FIG. 3. 1...Output terminal, Q3...Transistor, Q6
... Emitsuta follower transistor, R7, R8,
R14...Resistor, C3, C4...Capacitor, D
Z...Zener diode.
Claims (1)
く電圧が印加されこの電圧に基づいた電圧をエミ
ツタから出力する一方導電型のエミツタホロワト
ランジスタと、 ベースに前記エミツタホロワトランジスタのエ
ミツタ電圧が印加されてオン、オフし垂直帰線期
間にコレクタから帰線消去用のパルスを出力する
他方導電型のスイツチングトランジスタとを具備
したことを特徴とする帰線消去回路。 (2) ベースに垂直偏向コイルの両端電圧に基づ
く電圧が印加されてオン、オフし垂直帰線期間に
コレクタから帰線消去用のパルスを出力するスイ
ツチングトランジスタと、 ツエナー電圧の温度係数が前記スイツチングト
ランジスタのベース・エミツタ間電圧の温度係数
とは逆極性であり、前記スイツチングトランジス
タのエミツタと基準電位点との間に接続され電圧
源から抵抗を介してバイアス電流が供給されて前
記スイツチングトランジスタのエミツタにツエナ
ー電圧を与えるツエナーダイオードとを具備した
ことを特徴とする帰線消去回路。[Claims for Utility Model Registration] (1) A single conductivity type emitter follower transistor to which a voltage based on the voltage across the vertical deflection coil is applied to the base and outputs a voltage based on the voltage from the emitter; A retrace line characterized by comprising a switching transistor of the other conductivity type which turns on and off when an emitter voltage of the emitter follower transistor is applied and outputs a pulse for blanking from the collector during a vertical retrace period. Erasing circuit. (2) A switching transistor whose base is applied with a voltage based on the voltage across the vertical deflection coil, turns on and off, and outputs a pulse for blanking from the collector during the vertical blanking period, and a switching transistor whose temperature coefficient of Zener voltage is as above. The polarity is opposite to the temperature coefficient of the base-emitter voltage of the switching transistor, and a bias current is supplied from a voltage source connected between the emitter of the switching transistor and a reference potential point through a resistor to and a Zener diode that applies a Zener voltage to the emitter of a switching transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15077788U JPH0272075U (en) | 1988-11-21 | 1988-11-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15077788U JPH0272075U (en) | 1988-11-21 | 1988-11-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0272075U true JPH0272075U (en) | 1990-06-01 |
Family
ID=31424220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15077788U Pending JPH0272075U (en) | 1988-11-21 | 1988-11-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0272075U (en) |
-
1988
- 1988-11-21 JP JP15077788U patent/JPH0272075U/ja active Pending