JPS63144718U - - Google Patents
Info
- Publication number
- JPS63144718U JPS63144718U JP3673587U JP3673587U JPS63144718U JP S63144718 U JPS63144718 U JP S63144718U JP 3673587 U JP3673587 U JP 3673587U JP 3673587 U JP3673587 U JP 3673587U JP S63144718 U JPS63144718 U JP S63144718U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate
- transistor
- waveform
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図は本考案の実施例増幅回路の回路図、第
２図は本考案の実施例増幅回路の入力信号とゲー
トパルスとバイアス電圧との関係を示す図、第３
図は従来技術のトランス結合シングル電力増幅回
路例図、第４図は従来技術のトランス結合プツシ
ユプル電力増幅回路の１例の回路図、第５図はト
ランジスタのＶＢＥ―ＩＣ特性の１例を示す図で
ある。
１…波形整形回路、２…遅延回路、３…ゲート
回路、Ｒ１，Ｒ２，Ｒ３，Ｒ４，Ｒ５，Ｒ６，Ｒ
７，Ｒ８，Ｒ９，Ｒ１０…抵抗器、Ｃ１，Ｃ２…
コンデンサ、ＲＬ１，ＲＬ２，ＲＬ３…負荷、Ｔ
１，Ｔ３，Ｔ５…入力トランス、Ｔ２，Ｔ４，Ｔ
６…出力トランス、ＴＲ１，ＴＲ２，ＴＲ３，Ｔ
Ｒ４…トランジスタ、Ｖｃ…電源、ＧＮＤ…グラ
ンド、ＩＣ…トランジスタのコレクタ電流、ＶＢ
Ｅ…トランジスタのベース・エミツタ間電圧。
FIG. 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between input signals, gate pulses, and bias voltages of the amplifier circuit according to an embodiment of the present invention.
The figure shows an example of a conventional transformer-coupled single power amplifier circuit, FIG. 4 is a circuit diagram of an example of a conventional transformer-coupled push-pull power amplifier circuit, and FIG. 5 shows an example of VBE-IC characteristics of a transistor. It is. DESCRIPTION OF SYMBOLS 1...Waveform shaping circuit, 2...Delay circuit, 3...Gate circuit, R1, R2 , R3 , R4 , R5 , R6 , R
7 , R8 , R9 , R10 ...Resistor, C1 , C2 ...
Capacitor, RL 1 , RL 2 , RL 3 ...Load, T
1 , T 3 , T 5 ... input transformer, T 2 , T 4 , T
6 ...Output transformer, TR 1 , TR 2 , TR 3 , T
R4 ...transistor, Vc ...power supply, GND...ground, IC...collector current of transistor, VB
E...Voltage between the base and emitter of the transistor.
Claims (1)
波形整形回路と；前記ゲートパルスで制御される
ゲート回路と；該ゲート回路が導通状態のときの
みトランジスタに所定のバイアスを与えるバイア
ス回路と；を具備することを特徴とするトランジ
スタ増幅回路。 A waveform shaping circuit that shapes the waveform of an input signal and outputs a gate pulse; a gate circuit that is controlled by the gate pulse; and a bias circuit that applies a predetermined bias to the transistor only when the gate circuit is in a conductive state. A transistor amplifier circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673587U JPS63144718U (en) | 1987-03-13 | 1987-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673587U JPS63144718U (en) | 1987-03-13 | 1987-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144718U true JPS63144718U (en) | 1988-09-22 |
Family
ID=30847421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3673587U Pending JPS63144718U (en) | 1987-03-13 | 1987-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144718U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037914B2 (en) * | 1977-08-09 | 1985-08-29 | シチズン時計株式会社 | Electronic clock frequency adjustment device |
-
1987
- 1987-03-13 JP JP3673587U patent/JPS63144718U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037914B2 (en) * | 1977-08-09 | 1985-08-29 | シチズン時計株式会社 | Electronic clock frequency adjustment device |
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