JPS63144717U - - Google Patents
Info
- Publication number
- JPS63144717U JPS63144717U JP3673487U JP3673487U JPS63144717U JP S63144717 U JPS63144717 U JP S63144717U JP 3673487 U JP3673487 U JP 3673487U JP 3673487 U JP3673487 U JP 3673487U JP S63144717 U JPS63144717 U JP S63144717U
- Authority
- JP
- Japan
- Prior art keywords
- bias
- pulse
- circuit
- transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の実施例のトランジスタ増幅回
路の回路図、第２図は第１図のトランジスタ増幅
回路の各部の動作波形を示す図、第３図は従来技
術のトランス結合シングル電力増幅回路例図、第
４図は従来技術のトランス結合プツシユプル増幅
回路例図、第５図はトランジスタのＶＢＥ―ＩＣ
特性例の図である。
１…バイアスパルス発生回路、２…バイアス設
定回路、３…加算器、Ｒ１，Ｒ２，Ｒ４，Ｒ５，
Ｒ６，Ｒ７，Ｒ８，Ｒ９，Ｒ１０…抵抗器、Ｃ２
…コンデンサ、ＲＬ１，ＲＬ２，ＲＬ３…負荷、
Ｔ３，Ｔ５…入力トランス、Ｔ１，Ｔ４，Ｔ６…
出力トランス、ＴＲ１，ＴＲ２，ＴＲ３，ＴＲ４
…トランジスタ、ａ…入力信号波形、ｂ…バイア
スパルス、ｃ…バイアス設定回路出力波形、ｄ…
加算器出力波形、Ｖｃ…電源端子、ＧＮＤ…グラ
ンド。
Fig. 1 is a circuit diagram of a transistor amplifier circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing operating waveforms of each part of the transistor amplifier circuit of Fig. 1, and Fig. 3 is a conventional transformer-coupled single power amplifier circuit. Example diagram, Figure 4 is an example diagram of a conventional transformer-coupled push-pull amplifier circuit, and Figure 5 is a diagram of a transistor VBE-IC.
It is a figure of the example of a characteristic. 1... Bias pulse generation circuit, 2... Bias setting circuit, 3... Adder, R 1 , R 2 , R 4 , R 5 ,
R 6 , R 7 , R 8 , R 9 , R 10 ...Resistor, C 2
... Capacitor, RL 1 , RL 2 , RL 3 ... Load,
T 3 , T 5 ...input transformer, T 1 , T 4 , T 6 ...
Output transformer, TR 1 , TR 2 , TR 3 , TR 4
...transistor, a...input signal waveform, b...bias pulse, c...bias setting circuit output waveform, d...
Adder output waveform, Vc...power supply terminal, GND...ground.
Claims (1)
するバイアスパルス発生回路と；前記バイアスパ
ルスの電圧の大きさを設定するバイアス設定回路
と；該バイアス設定回路の出力パルスと入力信号
とを加算しその出力信号をトランジスタの入力に
伝える加算器と；を具備することを特徴とするト
ランジスタ増幅回路。 a bias pulse generation circuit that shapes an input signal and outputs a bias pulse; a bias setting circuit that sets the voltage magnitude of the bias pulse; and an output that adds the output pulse of the bias setting circuit and the input signal. A transistor amplifier circuit comprising: an adder for transmitting a signal to an input of a transistor;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673487U JPS63144717U (en) | 1987-03-13 | 1987-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3673487U JPS63144717U (en) | 1987-03-13 | 1987-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144717U true JPS63144717U (en) | 1988-09-22 |
Family
ID=30847419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3673487U Pending JPS63144717U (en) | 1987-03-13 | 1987-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144717U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037914B2 (en) * | 1977-08-09 | 1985-08-29 | シチズン時計株式会社 | Electronic clock frequency adjustment device |
-
1987
- 1987-03-13 JP JP3673487U patent/JPS63144717U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6037914B2 (en) * | 1977-08-09 | 1985-08-29 | シチズン時計株式会社 | Electronic clock frequency adjustment device |