JPH0333483U - - Google Patents

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Publication number
JPH0333483U
JPH0333483U JP9393389U JP9393389U JPH0333483U JP H0333483 U JPH0333483 U JP H0333483U JP 9393389 U JP9393389 U JP 9393389U JP 9393389 U JP9393389 U JP 9393389U JP H0333483 U JPH0333483 U JP H0333483U
Authority
JP
Japan
Prior art keywords
transistor
zener diode
circuit
voltage source
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9393389U
Other languages
Japanese (ja)
Other versions
JPH0753105Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989093933U priority Critical patent/JPH0753105Y2/en
Publication of JPH0333483U publication Critical patent/JPH0333483U/ja
Application granted granted Critical
Publication of JPH0753105Y2 publication Critical patent/JPH0753105Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、垂直偏向回路に組合わせた本考案の
実施例の回路ブロツク図、第2図は従来際の回路
ブロツク図である。 2……偏向ヨーク(偏向コイル)、11,12
……分圧抵抗、15……第2のツエナーダイオー
ド、16……第1のツエナーダイオード、17…
…第2の抵抗、18……第2のトランジスタ、1
9……第1のトランジスタ、20……第1の抵抗
、13……ポテンシヨメータ、14……差動増幅
器(制御手段)。
FIG. 1 is a circuit block diagram of an embodiment of the present invention combined with a vertical deflection circuit, and FIG. 2 is a conventional circuit block diagram. 2... Deflection yoke (deflection coil), 11, 12
...Voltage dividing resistor, 15... Second Zener diode, 16... First Zener diode, 17...
...Second resistor, 18...Second transistor, 1
9...first transistor, 20...first resistor, 13...potentiometer, 14...differential amplifier (control means).

Claims (1)

【実用新案登録請求の範囲】 (1) 受像管の垂直偏向回路の偏向回路と、前記
偏向コイルの低電位端に接続され、前記偏向コイ
ルに直流電流を流入し、もしくは流出させる定電
流回路と、前記定電流回路の出力電流の向きおよ
び大きさを連続的に制御する制御手段とを具備し
たことを特徴とする垂直ラスタセンタリング回路
。 (2) 偏向コイルの低電位端にコレクタを接続し
た第1のトランジスタと、この第1のトランジス
タのエミツタを第1の抵抗を介して第1の直流定
電圧源に接続し、さらにこの第1のトランジスタ
のベースにアノードが接続された第1のツエナー
ダイオードを備え、前記第1のトランジスタのコ
レクタに第2のトランジスタのコレクタを接続し
、この第2のトランジスタのエミツタを第2の抵
抗を介して第2の直流定電圧源に接続し、さらに
第2のトランジスタにカソードが接続された第2
のツエナーダイオードを備え、第1のトランジス
タと第2のトランジスタは相補型として構成され
、さらに前記第1のツエナーダイオードのカソー
ドと第2のツエナーダイオードとアノードを接続
し、この接続点を制御端子として構成してなる垂
直ラスタセンタリング回路。
[Claims for Utility Model Registration] (1) A deflection circuit of a vertical deflection circuit of a picture tube, and a constant current circuit that is connected to the low potential end of the deflection coil and causes direct current to flow into or out of the deflection coil. , and control means for continuously controlling the direction and magnitude of the output current of the constant current circuit. (2) A first transistor whose collector is connected to the low potential end of the deflection coil; an emitter of this first transistor is connected to a first DC constant voltage source via a first resistor; a first Zener diode whose anode is connected to the base of a transistor, a collector of a second transistor is connected to the collector of the first transistor, and an emitter of the second transistor is connected through a second resistor. a second constant voltage source, the second transistor having a cathode connected to the second constant voltage source;
a Zener diode, the first transistor and the second transistor are configured as complementary types, the cathode of the first Zener diode and the anode of the second Zener diode are connected, and this connection point is used as a control terminal. A vertical raster centering circuit consisting of:
JP1989093933U 1989-08-11 1989-08-11 Vertical raster centering circuit Expired - Lifetime JPH0753105Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989093933U JPH0753105Y2 (en) 1989-08-11 1989-08-11 Vertical raster centering circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989093933U JPH0753105Y2 (en) 1989-08-11 1989-08-11 Vertical raster centering circuit

Publications (2)

Publication Number Publication Date
JPH0333483U true JPH0333483U (en) 1991-04-02
JPH0753105Y2 JPH0753105Y2 (en) 1995-12-06

Family

ID=31643292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989093933U Expired - Lifetime JPH0753105Y2 (en) 1989-08-11 1989-08-11 Vertical raster centering circuit

Country Status (1)

Country Link
JP (1) JPH0753105Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003011796A (en) * 2001-06-28 2003-01-15 Tsubasa System Co Ltd Device and method for checking bill for vehicle inspection and maintenance, and program executable by computer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158971U (en) * 1986-03-28 1987-10-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158971U (en) * 1986-03-28 1987-10-08

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003011796A (en) * 2001-06-28 2003-01-15 Tsubasa System Co Ltd Device and method for checking bill for vehicle inspection and maintenance, and program executable by computer

Also Published As

Publication number Publication date
JPH0753105Y2 (en) 1995-12-06

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