JPH0415354U - - Google Patents
Info
- Publication number
- JPH0415354U JPH0415354U JP5664290U JP5664290U JPH0415354U JP H0415354 U JPH0415354 U JP H0415354U JP 5664290 U JP5664290 U JP 5664290U JP 5664290 U JP5664290 U JP 5664290U JP H0415354 U JPH0415354 U JP H0415354U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- signal
- circuit
- amplifier circuit
- deflection yoke
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は本考案の一実施例を示す図である。第
２図は各部の波形を示す図である。第３図は従来
回路を示す図である。第４図はノンインターレー
スとインターレースを説明するための図である。
１０ｂ……帰還入力端子、１０ｃ……垂直振幅
制御端子、１２……鋸歯状波作成回路、１２ａ…
…充放電コンデンサ（第１コンデンサ）、１２ｂ
……充放電制御トランジスタ（トランジスタ）、
１２ｃ……定電流回路、１４……差動増幅回路、
１６……増幅回路（電力増幅回路）、２０……帰
還回路、２２……直列回路、Ｃ４……第３コンデ
ンサ、Ｒ２……抵抗（第２抵抗）、ＤＹ……偏向
ヨーク、Ｃ２……カツプリングコンデンサ（第２
コンデンサ）、Ｒ２……抵抗（第１抵抗）。
FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing waveforms at various parts. FIG. 3 is a diagram showing a conventional circuit. FIG. 4 is a diagram for explaining non-interlace and interlace. 10b... Feedback input terminal, 10c... Vertical amplitude control terminal, 12... Sawtooth wave creation circuit, 12a...
...Charge/discharge capacitor (first capacitor), 12b
...charge/discharge control transistor (transistor),
12c... Constant current circuit, 14... Differential amplifier circuit,
16...Amplification circuit (power amplification circuit), 20...Feedback circuit, 22...Series circuit, C4...Third capacitor, R2...Resistor (second resistor), DY...Deflection yoke, C2...Cup Ring capacitor (second
capacitor), R2...resistor (first resistor).
Claims (1)
サ１２ａを、充・放電せしめて鋸歯状波信号を作
成するトランジスタ１２ｂと、 この鋸歯状波信号を一方の入力とし、帰還入力
端子１０ｂからの信号を他方の入力とする差動増
幅回路１４と、 この差動増幅回路１４からの信号を増幅する電
力増幅回路１６と、 この電力増幅回路１６により駆動される偏向ヨ
ークＤＹと、 この偏向ヨークＤＹとアース間に直列に接続さ
れた第２コンデンサＣ２と第１抵抗Ｒ２と、 この第２コンデンサＣ２の両端の信号より前記
帰還入力端子１０ｂへの信号を出力する帰還回路
２０と、 前記第１コンデンサ１２ａの電流量を決定する
定電流回路１２ｃを制御する垂直振幅制御端子１
０ｃと、 前記偏向ヨークＤＹと第２コンデンサＣ２との
接続点ロの信号を前記垂直振幅制御端子１０ｃに
出力する第３コンデンサＣ４と第２抵抗Ｒ１０の
直列回路２２と、 を備える垂直偏向出力回路。[Claims for Utility Model Registration] A transistor 12b that is driven by an input vertical pulse to charge and discharge the first capacitor 12a to create a sawtooth wave signal; A differential amplifier circuit 14 whose other input is a signal from the terminal 10b, a power amplifier circuit 16 which amplifies the signal from this differential amplifier circuit 14, and a deflection yoke DY driven by this power amplifier circuit 16. a second capacitor C2 and a first resistor R2 connected in series between the deflection yoke DY and the ground; a feedback circuit 20 that outputs a signal from the signal across the second capacitor C2 to the feedback input terminal 10b; a vertical amplitude control terminal 1 that controls a constant current circuit 12c that determines the amount of current flowing through the first capacitor 12a;
0c, and a series circuit 22 of a third capacitor C4 and a second resistor R10 that outputs a signal at a connection point RO between the deflection yoke DY and the second capacitor C2 to the vertical amplitude control terminal 10c. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5664290U JPH0744130Y2 (en) | 1990-05-30 | 1990-05-30 | Vertical deflection output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5664290U JPH0744130Y2 (en) | 1990-05-30 | 1990-05-30 | Vertical deflection output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0415354U true JPH0415354U (en) | 1992-02-07 |
| JPH0744130Y2 JPH0744130Y2 (en) | 1995-10-09 |
Family
ID=31580649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5664290U Expired - Lifetime JPH0744130Y2 (en) | 1990-05-30 | 1990-05-30 | Vertical deflection output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744130Y2 (en) |
-
1990
- 1990-05-30 JP JP5664290U patent/JPH0744130Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744130Y2 (en) | 1995-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |