JPH01173976A - Vertical deflection circuit - Google Patents
Vertical deflection circuitInfo
- Publication number
- JPH01173976A JPH01173976A JP32971087A JP32971087A JPH01173976A JP H01173976 A JPH01173976 A JP H01173976A JP 32971087 A JP32971087 A JP 32971087A JP 32971087 A JP32971087 A JP 32971087A JP H01173976 A JPH01173976 A JP H01173976A
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- circuit
- capacitor
- vertical
- vertical deflection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 230000001360 synchronised effect Effects 0.000 claims abstract description 8
- 238000007493 shaping process Methods 0.000 claims abstract description 7
- 230000010354 integration Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 8
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、垂直リニアリティを大幅に改善する垂直偏
向回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a vertical deflection circuit that significantly improves vertical linearity.
従来、CRTとしては管面が比較的丸いものが専ら使用
されていたが、最近では画面の見やすさ等を向上させる
目的でFS管が多用されつつある。Conventionally, CRTs with relatively round tube surfaces have been exclusively used, but recently, FS tubes have been increasingly used to improve the visibility of the screen.
しかし、FS管の場合、例えば従来の丸型の20インチ
CRTでR=850mmであった管面の曲率半径が21
インチCRTでR=1730mm程度と大きくなり、中
心部と周辺部における電子銃より射出された電子ビーム
が偏向コイル内で偏向される際の仮想中心、いわゆる偏
向中心から蛍光面までの距離の差が著しく大きくなるた
め、画面の垂直方向の直線性が悪くなっていた。However, in the case of an FS tube, for example, the radius of curvature of the tube surface is 21 mm, which is R = 850 mm in a conventional round 20-inch CRT.
For an inch CRT, R = approximately 1730 mm, which is large, and the difference in distance between the center and the periphery from the virtual center when the electron beam emitted from the electron gun is deflected within the deflection coil, the so-called deflection center, to the phosphor screen. As the screen became significantly larger, the vertical linearity of the screen deteriorated.
このような画面の垂直方向の直線性を良好なものとする
ための補正、いわゆる垂直リニアリティ補正を行う従来
の垂直偏向回路としては、例えば特開昭61−1179
77号公報に示されるようなもののほかに、種々のもの
が提案されている。As a conventional vertical deflection circuit that performs correction to improve the vertical linearity of the screen, so-called vertical linearity correction, for example, Japanese Patent Application Laid-Open No. 1179-1983
In addition to the one shown in Publication No. 77, various other ones have been proposed.
第3図は特開昭61−117977号公報に記載された
従来の垂直偏向回路を示す図である。FIG. 3 is a diagram showing a conventional vertical deflection circuit described in Japanese Patent Application Laid-open No. 117977/1983.
この図において、1は垂直発振段、2は垂直駆動および
出力段、3は垂直偏向コイル、4は直流阻止用コンデン
サ、5は掃通用抵抗器、6〜8は第1〜第3の可変抵抗
器、9は直列抵抗器、1o、11は第1および第2の結
合コンデンサ、12は負荷抵抗器、13は発振出力トラ
ンジスタ、14.15は直流源、16は直流電源端子、
17は反転増幅器である。この垂直偏向回路では、垂直
偏向コイル3に直列接続された直流阻止用コンデンサ4
の一端と第3の可変抵抗器8から、それぞれ第1の帰還
ループ、第2の帰還ループを介して、第4図(a)に示
すような鋸歯状波電流と第4図(b)に示すような反転
されたパラボラ電流とを取り出した後、重畳して第4図
(C)に示すような波形として垂直駆動および出力段2
の入力端に帰還することによって3字補正を行っている
。また、第1〜第3の可変抵抗器6〜8を調整すること
により、補正量および補正範囲を調節することができる
。In this figure, 1 is a vertical oscillation stage, 2 is a vertical drive and output stage, 3 is a vertical deflection coil, 4 is a DC blocking capacitor, 5 is a sweeping resistor, and 6 to 8 are first to third variable resistors. 9 is a series resistor, 1o and 11 are first and second coupling capacitors, 12 is a load resistor, 13 is an oscillation output transistor, 14.15 is a DC source, 16 is a DC power supply terminal,
17 is an inverting amplifier. In this vertical deflection circuit, a DC blocking capacitor 4 is connected in series to a vertical deflection coil 3.
A sawtooth wave current as shown in FIG. 4(a) and a sawtooth wave current as shown in FIG. 4(b) are generated from the one end and the third variable resistor 8 through the first feedback loop and the second feedback loop, respectively. After extracting the inverted parabolic current as shown in FIG. 4(C), the vertical drive and output stage 2
Three-character correction is performed by feeding back to the input terminal of. Further, by adjusting the first to third variable resistors 6 to 8, the correction amount and correction range can be adjusted.
しかし、上記のような従来の垂直偏向回路では、鋸歯状
波電流を垂直偏向コイル3に流した際に直流阻止用コン
デンサ4の両端に発生するパラボラ波形を帰還して使用
しているため、実際に垂直リニアリティ補正(3字補正
)を行った場合、発生するパラボラ波形が変化し、十分
な補正を行えないという問題点があった。However, in the conventional vertical deflection circuit as described above, the parabolic waveform generated across the DC blocking capacitor 4 when a sawtooth wave current is passed through the vertical deflection coil 3 is fed back and used. When vertical linearity correction (three-character correction) is performed on the image, the generated parabolic waveform changes and there is a problem in that sufficient correction cannot be performed.
また、上記の垂直偏向回路以外に特開昭55−4777
3号、60−127877号、62−26978号、実
開昭56−145165号公報等にも垂直リニアリティ
の補正について述べられているが、それらの何れにおい
ても曲率半径の大ぎなFS管への適用が考慮されていな
いため、FS管に適用しても十分な効果が得られないと
いう問題点があった。In addition to the above vertical deflection circuit, there is also a
No. 3, No. 60-127877, No. 62-26978, Japanese Utility Model Application Publication No. 145165/1987, etc. also mention correction of vertical linearity, but none of them apply to FS tubes with a large radius of curvature. Since this method is not taken into account, there is a problem in that sufficient effects cannot be obtained even when applied to FS pipes.
この発明は、かかる問題点を解決するためになされたも
ので、FS管に適用しても十分に垂直リニアリティの補
正を行うことが可能な垂直偏向回路を得ることを目的と
する。The present invention was made in order to solve such problems, and an object of the present invention is to obtain a vertical deflection circuit that can sufficiently correct vertical linearity even when applied to an FS tube.
この発明に係る垂直偏向回路は、鋸歯状波信号により変
調された定電流波形を出力する定電流回路と、この定電
流回路の出力端に接続され、垂直同期信号に同期した駆
動パルスによりスイッチングを行う素子と、定電流回路
の出力端に接続されるとともに、素子と並列に接続され
た電流積分用のキャパシタと、このキャパシタと並列に
接続された分流用の可変抵抗器とからなる波形整形回路
を備えたものである。The vertical deflection circuit according to the present invention includes a constant current circuit that outputs a constant current waveform modulated by a sawtooth wave signal, and a constant current circuit that is connected to the output end of the constant current circuit and performs switching by a drive pulse synchronized with a vertical synchronization signal. A waveform shaping circuit consisting of a current integration element connected to the output end of a constant current circuit and in parallel with the element, and a shunt variable resistor connected in parallel with this capacitor. It is equipped with the following.
(作用)
この発明においては、定電流回路を流れる電流が周期の
前半では主として電流積分用のキャパシタに流れ、その
両端の電圧は上向きのパラボラ状に上昇する。また、周
期の後半では電流が分流用の可変抵抗器に主として流れ
るようになり、電流積分用のキャパシタの両端の電圧は
下向ぎのパラボラ状に上昇する。(Function) In the present invention, the current flowing through the constant current circuit mainly flows through the current integrating capacitor in the first half of the cycle, and the voltage across the capacitor increases in an upward parabolic manner. In addition, in the latter half of the cycle, the current mainly flows through the shunt variable resistor, and the voltage across the current integration capacitor increases in a downward parabolic manner.
第1図はこの発明の垂直偏向回路の一実施例を示す図で
ある。FIG. 1 is a diagram showing an embodiment of the vertical deflection circuit of the present invention.
この図において、21は垂直同期信号に同期した駆動パ
ルスによりスイッチングを行うトランジスタ、22.2
8は電流積分用のキャパシタ、23は電流値を可変でき
る直流の定電流源、24は直流電圧源で、増幅器25.
鋸歯状波信号で変調される定電流駆動用のトランジスタ
26.エミッタ電源を検出する抵抗器27によって構成
される定電流回路150の最小電流値を決定する。29
は垂直同期信号に同期した駆動パルスによりスイッチン
グを行うトランジスタ、30は分流用の可変抵抗器、3
1.34は増幅器、32は可変抵抗器、33は画面の位
置を決定する直流電圧源、35は垂直偏向コイル、36
は前記垂直偏向コイル35に流れる電流値を検出する抵
抗器、100は鋸歯状波信号発生回路、200は波形整
形回路、300は垂直偏向コイル駆動回路である。In this figure, 21 is a transistor that performs switching by a drive pulse synchronized with a vertical synchronization signal, 22.2
8 is a capacitor for current integration, 23 is a DC constant current source whose current value can be varied, 24 is a DC voltage source, and amplifier 25.
A constant current driving transistor 26 modulated by a sawtooth wave signal. The minimum current value of the constant current circuit 150 constituted by the resistor 27 that detects the emitter power supply is determined. 29
3 is a transistor that performs switching by a drive pulse synchronized with a vertical synchronization signal; 30 is a variable resistor for shunting; 3
1.34 is an amplifier, 32 is a variable resistor, 33 is a DC voltage source that determines the position of the screen, 35 is a vertical deflection coil, 36
100 is a sawtooth wave signal generating circuit, 200 is a waveform shaping circuit, and 300 is a vertical deflection coil driving circuit.
また、第2図(a)〜(d)は第1図に示した垂直偏向
回路における主要な信号の波形図である。2(a) to 2(d) are waveform diagrams of main signals in the vertical deflection circuit shown in FIG. 1.
次に動作について説明する。Next, the operation will be explained.
トランジスタ21.29はベースから入力される第2図
(a)に示すような垂直同期信号に同期゛した駆動パル
スによって、垂直帰線期間に“オン”どなる。あらかじ
め定電流源23により充電されているキャパシタ22は
、トランジスタ21の”オン”により放電させられたの
ち、“オフ”により再度充電されるためその両端の電圧
の変化は第2図(b)に示すようになる。すなわち、鋸
歯状波信号が発生されたことになり、増幅器25は、反
転入力端に入力されるこの鋸歯状波信号の電圧の変化に
対応してトランジスタ26を変調する。これにより、ト
ランジスタ26のエミッターコレクタ間の電流は第2図
(b)に示すように変化することになる。The transistors 21 and 29 are turned "on" during the vertical retrace period by a drive pulse synchronized with a vertical synchronizing signal as shown in FIG. 2(a) inputted from the base. The capacitor 22, which has been charged in advance by the constant current source 23, is discharged when the transistor 21 is turned on and then charged again when it is turned off, so the change in voltage across it is as shown in Figure 2(b). It comes to show. That is, a sawtooth wave signal is generated, and the amplifier 25 modulates the transistor 26 in response to a change in the voltage of the sawtooth signal input to the inverting input terminal. As a result, the emitter-collector current of the transistor 26 changes as shown in FIG. 2(b).
いま、可変抵抗器30がキャパシタ28と並列に接続さ
れていないものとすると、トランジスタ29が“オフ”
となっている間、第2図(b)に示した波形の電流でキ
ャパシタ2日が充電されることになり、キャパシタ28
の両端の電圧の変化は第2図(C)に示すようになるが
、実際には可変抵抗器30が接続されているため、電流
は分流されることになる。そして、可変抵抗器30の抵
抗値が小さいと、キャパシタ28の両端の電圧が高くな
る程電流が可変抵抗器30側に流れやすくなり、キャパ
シタ28の両端の電圧は第2図(d)に示すように完全
に3字補正された鋸歯状に変化する。Now, assuming that the variable resistor 30 is not connected in parallel with the capacitor 28, the transistor 29 is "off".
During this period, the capacitor 28 is charged with the current waveform shown in Fig. 2(b), and the capacitor 28
The change in voltage across both ends is as shown in FIG. 2(C), but since the variable resistor 30 is actually connected, the current will be shunted. If the resistance value of the variable resistor 30 is small, the higher the voltage across the capacitor 28, the easier the current will flow toward the variable resistor 30, and the voltage across the capacitor 28 will be as shown in FIG. 2(d). It changes into a sawtooth shape with complete three-character correction.
したがって、この信号を増幅器31でバッファし、増幅
器34で垂直偏向コイル35を定電流駆動すれば、FS
管に対しても垂直リニアリティの良好な画面を得ること
ができる。Therefore, if this signal is buffered by the amplifier 31 and the vertical deflection coil 35 is driven at a constant current by the amplifier 34, the FS
A screen with good vertical linearity can be obtained even with respect to the tube.
この実施例の垂直偏向回路では、画面の垂直寸法が可変
抵抗器32と抵抗器36の抵抗比で決定され、画面の上
下位置は直流電圧源33の電圧によって決定される。In the vertical deflection circuit of this embodiment, the vertical dimension of the screen is determined by the resistance ratio of the variable resistor 32 and the resistor 36, and the vertical position of the screen is determined by the voltage of the DC voltage source 33.
また、垂直リニアリティは画面の上部と下部でそれぞれ
独立して調整することが可能であり、定電流源23の電
流値を調整すれば第2図(d)の波形の前半、すなわち
画面の上部のりニアリティ、可変抵抗器30の抵抗値を
調整すれば第2図(d)の波形の後半、すなわち、画面
の下部のりニアリティの調整を行うことができる。例え
ば、定電流源23の電流値を増せば波形の前半での3字
補正量が大きくなり、可変抵抗器30の抵抗値を減少さ
せれば波形の後半での3字補正量が大きくなる。In addition, the vertical linearity can be adjusted independently at the top and bottom of the screen, and by adjusting the current value of the constant current source 23, the first half of the waveform in Fig. 2(d), that is, the vertical linearity at the top of the screen, can be adjusted independently. By adjusting the linearity and the resistance value of the variable resistor 30, the linearity of the latter half of the waveform shown in FIG. 2(d), that is, the lower part of the screen, can be adjusted. For example, if the current value of the constant current source 23 is increased, the amount of 3-character correction in the first half of the waveform will be increased, and if the resistance value of the variable resistor 30 is decreased, the amount of 3-character correction in the latter half of the waveform will be increased.
また、垂直偏向コイル駆動回路300からのフィードバ
ックをDC成分、パラボラ成分等に分離する必要がない
ため、従来のものと比較して簡単な回路で実現でき、周
波数特性が直流までフラットな出力段を構成しやすく、
インタレースにて動作する場合において直流特性が悪く
、偶数フィールドと奇数フィールドのラスク間隔が同一
にならない、いわゆるベアリング等の発生しにくい諸特
性に優れた垂直偏向回路を実現することが可能になる。In addition, since there is no need to separate the feedback from the vertical deflection coil drive circuit 300 into DC components, parabolic components, etc., it can be realized with a simpler circuit than conventional ones, and an output stage with flat frequency characteristics up to DC can be realized. Easy to configure;
It is possible to realize a vertical deflection circuit that has poor direct current characteristics when operating in an interlaced manner, and has excellent characteristics in which so-called bearings, such as the rask spacing between even and odd fields are not the same, are less likely to occur.
特に、鋸歯状波信号発生回路100としてはTV用のI
Cに内蔵されているものを流用できるため、回路構成を
さらに簡単にすることができる。In particular, as the sawtooth wave signal generation circuit 100, the I
Since components built in C can be used, the circuit configuration can be further simplified.
また、上記実施例ではバイポーラトランジスタを用いて
回路を構成したが、この発明はこれに限定されるもので
なくFET等を用いて構成してもよい。Further, in the above embodiment, the circuit was constructed using bipolar transistors, but the present invention is not limited to this, and may be constructed using FETs or the like.
また、さらにFS管のみならず、110°偏同等の広角
偏向のCRTにも適用可能であり、高直線性を得る事が
できることはいうまでもない。Furthermore, it goes without saying that it is applicable not only to FS tubes but also to CRTs with a wide-angle deflection equivalent to 110° deflection, and high linearity can be obtained.
この発明は以上説明したとおり、鋸歯状波信号により変
調された定電流波形を出力する定電流回路と、この定電
流回路の出力端に接続され、垂直同期信号に同期した駆
動パルスによりスイッチングを行う素子と、定電流回路
の出力端に接続されるとともに、素子と並列に接続され
た電流積分用のキャパシタと、このキャパシタと並列に
接続された分流用の可変抵抗器とからなる波形整形回路
を備えたので、はぼ完全な3字補正を行うことができる
うえ、画面上部と下部のりニアリティを独立して調整で
き、FSS管用用時も十分な直線性を得ることができる
という効果がある。As explained above, this invention includes a constant current circuit that outputs a constant current waveform modulated by a sawtooth wave signal, and a constant current circuit that is connected to the output end of this constant current circuit and performs switching using a drive pulse synchronized with a vertical synchronization signal. A waveform shaping circuit consisting of an element, a current integration capacitor connected to the output end of a constant current circuit and in parallel with the element, and a shunt variable resistor connected in parallel with this capacitor. With this feature, not only can a complete three-character correction be performed, but also the linearity at the top and bottom of the screen can be adjusted independently, allowing for sufficient linearity to be obtained even when used for FSS tubes.
第1図はこの発明の垂直偏向回路の一実施例を示す図、
第2図(a)〜(d)はこの発明の垂直偏向回路の動作
を説明するための図、第3図は従来の垂直偏向回路を示
す図、第4図(a)〜(C)は従来の垂直偏向回路の動
作を説明するための図である。
図中、21.26.29はトランジスタ、22.28は
キャパシタ、23は定電流源、24゜33は直流電圧源
、25.31.34は増幅器、30.32は可変抵抗器
、35は垂直偏向コイル、100は鋸歯状波信号発生回
路、150は定電流回路、200は波形整形回路、30
0は垂直偏向コイル駆動回路である。
第2図
第3図
第4図FIG. 1 is a diagram showing an embodiment of the vertical deflection circuit of the present invention;
FIGS. 2(a) to (d) are diagrams for explaining the operation of the vertical deflection circuit of the present invention, FIG. 3 is a diagram showing a conventional vertical deflection circuit, and FIGS. 4(a) to (C) are diagrams for explaining the operation of the vertical deflection circuit of the present invention. FIG. 3 is a diagram for explaining the operation of a conventional vertical deflection circuit. In the figure, 21, 26, 29 are transistors, 22, 28 are capacitors, 23 is a constant current source, 24° 33 is a DC voltage source, 25, 31, 34 is an amplifier, 30, 32 is a variable resistor, and 35 is a vertical Deflection coil, 100 a sawtooth signal generation circuit, 150 a constant current circuit, 200 a waveform shaping circuit, 30
0 is a vertical deflection coil drive circuit. Figure 2 Figure 3 Figure 4
Claims (1)
電流回路と、この定電流回路の出力端に接続され、垂直
同期信号に同期した駆動パルスによりスイッチングを行
う素子と、前記定電流回路の出力端に接続されるととも
に、前記素子と並列に接続された電流積分用のキャパシ
タと、このキャパシタと並列に接続された分流用の可変
抵抗器とからなる波形整形回路を備えたことを特徴とす
る垂直偏向回路。a constant current circuit that outputs a constant current waveform modulated by a sawtooth wave signal; an element connected to the output end of the constant current circuit that performs switching using a drive pulse synchronized with a vertical synchronization signal; The device is characterized by comprising a waveform shaping circuit connected to the output end and consisting of a current integration capacitor connected in parallel with the element, and a shunting variable resistor connected in parallel with this capacitor. vertical deflection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32971087A JPH078010B2 (en) | 1987-12-28 | 1987-12-28 | Vertical deflection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32971087A JPH078010B2 (en) | 1987-12-28 | 1987-12-28 | Vertical deflection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01173976A true JPH01173976A (en) | 1989-07-10 |
JPH078010B2 JPH078010B2 (en) | 1995-01-30 |
Family
ID=18224405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32971087A Expired - Lifetime JPH078010B2 (en) | 1987-12-28 | 1987-12-28 | Vertical deflection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH078010B2 (en) |
-
1987
- 1987-12-28 JP JP32971087A patent/JPH078010B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH078010B2 (en) | 1995-01-30 |
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