JPH0271564A - Memory device - Google Patents
Memory deviceInfo
- Publication number
- JPH0271564A JPH0271564A JP63222614A JP22261488A JPH0271564A JP H0271564 A JPH0271564 A JP H0271564A JP 63222614 A JP63222614 A JP 63222614A JP 22261488 A JP22261488 A JP 22261488A JP H0271564 A JPH0271564 A JP H0271564A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor layer
- electrode
- capacity
- change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 6
- 230000000717 retained effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003070 TaOx Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- DVRDHUBQLOKMHZ-UHFFFAOYSA-N chalcopyrite Chemical compound [S-2].[S-2].[Fe+2].[Cu+2] DVRDHUBQLOKMHZ-UHFFFAOYSA-N 0.000 description 1
- 229910052951 chalcopyrite Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- -1 polycides Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は記憶装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a storage device.
〔従来の技術ｊ
従来、ＩＥＤＭ８７Ｐ、５６０〜５６３に記載されてい
るような、通常のＭＯ５Ｉ−ランジスタにコントロール
ゲート、フローティングゲート１．肖去ゲートを具備せ
しめた記・は装置が知られていた。[Conventional technology j Conventionally, as described in IEDM87P, 560-563, a control gate, a floating gate 1. A device equipped with a death gate was known.
〔発明が解決しようとする課題）
しかし、従来の記憶装置は次のような課題を有していた
。第１に構造が複雑であるため１ビツトを記憶するに必
要な面積を広（取らな（ではならないため、記憶容量を
上げることができない、第２に、複雑な工程を要するの
でコスト高となりビット単価を下けれないこと、である
。[Problems to be Solved by the Invention] However, conventional storage devices have had the following problems. Firstly, because the structure is complex, the area required to store one bit cannot be increased, so the storage capacity cannot be increased.Secondly, it requires a complicated process, which increases the cost. The problem is that the unit price cannot be lowered.
本発明は従来のこのような課題を解決するもので目的と
するところは、大きな記憶容量を持ち、ビット単価の安
い記憶装置を提供することである。The present invention is intended to solve these conventional problems, and an object of the present invention is to provide a storage device having a large storage capacity and a low cost per bit.
〔課題を解決するための手段］
本発明の記憶装置は、半導体基板上に形成された第１の
絶縁層、前記絶縁層上に形成された第１の電極、前記第
１の電極上に形成された半導体層、前記半導体層上に形
成された第２の絶縁層、前記第２の絶縁層上に形成され
た第３の絶縁層、前記第３の絶縁層上に形成された第２
の電極を具備したことを特徴とする。[Means for Solving the Problems] A memory device of the present invention includes a first insulating layer formed on a semiconductor substrate, a first electrode formed on the insulating layer, and a first electrode formed on the first electrode. a second insulating layer formed on the semiconductor layer, a third insulating layer formed on the second insulating layer, and a second insulating layer formed on the third insulating layer.
It is characterized by being equipped with the following electrodes.
［実 施 例］
以下に、本発明の実施例を図面に基づいて説明する。第
１図（ａ）、（ｂ）は本発明にかかる記憶装置の構成を
示す、第１図（ｂ）は同図Ａ−Ｂ間の断面を示す、シリ
コン基板から成る半導体基板１上にＳ ｉ Ｏｗから成
る第１の絶縁層２が設けられており、第１の絶縁層２上
にＭＯから成る第１のｉｉｔ極３が設けられており、第
１の電極３上に非単結晶シリコンから成る半導体層４が
設けられており、半導体層４上にＳｉ Ｏｘかも成る第
２の絶縁層５が設けられており、第２の絶縁層５上にＳ
ｉＮｘから成る第３の絶縁層６が設けられており、第３
の絶縁層６上にドープドシリコンから成る第２の電極７
が設けられている。[Example] Examples of the present invention will be described below based on the drawings. FIGS. 1(a) and 1(b) show the structure of a memory device according to the present invention, and FIG. 1(b) shows a cross section taken along line A-B in the same figure. A first insulating layer 2 made of iOw is provided, a first IIT electrode 3 made of MO is provided on the first insulating layer 2, and a first IIT electrode 3 made of MO is provided on the first electrode 3. A semiconductor layer 4 made of SiOx is provided, a second insulating layer 5 made of SiOx is provided on the semiconductor layer 4, and a second insulating layer 5 made of SiOx is provided on the second insulating layer 5.
A third insulating layer 6 made of iNx is provided.
A second electrode 7 made of doped silicon is disposed on the insulating layer 6 of
is provided.
第１の電極３と第２の電ｔｆｉ７の間に電圧が印加され
、半導体層４あるいは第２の電極７から電荷が放出され
、前記電荷が第３の絶縁層６中の第２の絶縁層５の界面
付近に存在するトラップ準位にトラップされる。トラッ
プされた電荷により半導体層４のバンドの曲がりが生じ
、半導体層４の電気的容量が変化する。これは第１と第
２の電極３．７間の電気的容量の変化を生じさせる。前
記電気的容量の変化を用いてデータの有無を記憶するこ
とができる。前記トラップされた電荷は電圧を切った後
も不揮発性を持って保持されるため、不揮発性の記憶装
置となる。また、トラップされた電荷の有無によって生
じる電荷による半導体層４と第２及び第３の絶縁層５．
６のバンドの曲がりに起因する第１と第２の電極３．７
間の電気抵抗の変化を用いてデータの記憶に用いても良
い。A voltage is applied between the first electrode 3 and the second electrode tfi7, charges are released from the semiconductor layer 4 or the second electrode 7, and the charges are transferred to the second insulating layer in the third insulating layer 6. It is trapped in the trap level existing near the interface of 5. The trapped charges cause the band of the semiconductor layer 4 to bend, and the electrical capacitance of the semiconductor layer 4 changes. This causes a change in the electrical capacitance between the first and second electrodes 3.7. The presence or absence of data can be stored using the change in electrical capacitance. Since the trapped charges are held nonvolatile even after the voltage is turned off, the device becomes a nonvolatile memory device. In addition, the semiconductor layer 4 and the second and third insulating layers 5 .
6. The first and second electrodes due to the bending of the band 3.7
The change in electrical resistance between the two may be used to store data.
第１図（ａ）、（ｂ）において半導体基板１として用い
られる基板はシリコン基板に限る必要は無く、例えばＩ
ＩＩ −Ｖ族、あるいはＴＩ −ＩＶ族化合物半導体基
板やカルコパイライト基板を用いても良い。The substrate used as the semiconductor substrate 1 in FIGS. 1(a) and 1(b) is not limited to a silicon substrate; for example, an I
A II-V group or TI-IV group compound semiconductor substrate or chalcopyrite substrate may be used.
また第１及び第２及び第３の絶縁層２．５．６に用いら
れる材料はＳ ｉ Ｏ２やＳｉＮｘに限る必要は無く、
例えば５ｉＯ１ＳｉＯＮ、５ｉｓＮａ 、ＴａＯｘなど
を用いても良い。半導体層４から放出された電荷を用い
る際は第２の絶縁Ｎ５の厚みはトンネル電流が生じる程
度に薄＜（〈１００Ａ）にすることが望ましい、また、
半導体層４に用いられる材料は非単結晶シリコンに限る
必要は無く、例えば単結晶シリコンやＩｒｒ −Ｖ族、
ＩＩ−ＩＶ族化合物半導体を単結晶、非単結晶の状態で
用いても良い、非単結晶で用いる際は、水素やハロゲン
原子を用いてトラップ準位を補償すると半導体層４の電
気的容量変化が大きくなり特に有効である。また、半導
体層４に用いられる材料の電気的特性はｎ型、ｐ型、イ
ントリンシックのいずれでも良い、また、半導体層４の
膜厚は半導体層４が本来持つ空乏層の厚みよりも薄いこ
とが望ましい。Furthermore, the materials used for the first, second, and third insulating layers 2.5.6 are not limited to SiO2 or SiNx;
For example, 5iO1SiON, 5isNa, TaOx, etc. may be used. When using the charge emitted from the semiconductor layer 4, it is desirable that the thickness of the second insulating layer N5 is as thin as <(<100 A) to generate a tunnel current.
The material used for the semiconductor layer 4 is not limited to non-single-crystal silicon, and may include, for example, single-crystal silicon, Irr-V group,
Group II-IV compound semiconductors may be used in a single crystal or non-single crystal state. When used in a non-single crystal state, the electrical capacitance of the semiconductor layer 4 will change if the trap level is compensated using hydrogen or halogen atoms. is particularly effective. Further, the electrical characteristics of the material used for the semiconductor layer 4 may be n-type, p-type, or intrinsic, and the thickness of the semiconductor layer 4 must be thinner than the thickness of the depletion layer that the semiconductor layer 4 originally has. is desirable.
また、第１及び第２の電極３．７に用いられる材料はＭ
ｏやドープドシリコンに限る必要は無く１例えばＡＩな
どの金属、シリサイド、高融点金属、ポリサイド、半導
体を用いても良い。Furthermore, the material used for the first and second electrodes 3.7 is M
There is no need to limit the material to silicon or doped silicon; for example, metals such as AI, silicides, high melting point metals, polycides, and semiconductors may be used.
第２図（ａ）、（ｂ）に本発明の記憶装置をマトリクス
状に配置した記憶装置を示す、第２図（ｂ）は同図（ａ
）のＡ−Ｂにおける断面図であり同図（ａ）は上視図で
ある。シリコン基板から成る半導体基板１上にＳ ｉ
Ｏｚから成る第１の絶縁層２が設けられており、第１の
絶縁層２上にストライブ状の第１の電極３が設けられて
おり、第１の電極３上に非単結晶シリコンから成る半導
体層４、半導体層４上に５ｉｆ２から成る第２の絶縁層
４、第２の絶縁層４上にＳｉＮｘから成る第３の絶縁層
６、第３の絶縁層、上にドープドシリコンから成るスト
ライプ状の第２の電極７が設けられている。第１及び第
２の電極２．７は半導体基板１上に設けられた集積回路
より成るロウデコーダおよびセンスアンプ、Ｉ１０ゲー
ト、カラムデコーダへ結ばれている。ロウデコーダ、セ
ンスアンプ、Ｉ１０ゲート、カラムデコーダについては
特に図示しないが、通常の半導体プロセスを持って形成
されるＭＯＳトランジスタ、バイポーラトランジスタ、
ダイオード、抵抗、容量より構成されている。FIGS. 2(a) and 2(b) show a storage device in which storage devices of the present invention are arranged in a matrix, and FIG.
), and (a) is a top view. S i on a semiconductor substrate 1 made of a silicon substrate
A first insulating layer 2 made of OZ is provided, a strip-shaped first electrode 3 is provided on the first insulating layer 2, and a first electrode 3 made of non-monocrystalline silicon is provided on the first electrode 3. a second insulating layer 4 made of 5if2 on the semiconductor layer 4; a third insulating layer 6 made of SiNx on the second insulating layer 4; A striped second electrode 7 is provided. The first and second electrodes 2.7 are connected to a row decoder and a sense amplifier, an I10 gate, and a column decoder, each of which is an integrated circuit provided on the semiconductor substrate 1. Row decoders, sense amplifiers, I10 gates, and column decoders are not particularly shown, but they are MOS transistors, bipolar transistors, and bipolar transistors formed using normal semiconductor processes.
It consists of a diode, a resistor, and a capacitor.
第２図（ａ）、（ｂ）に示すように本発明の記憶装置の
記憶容量は１μｍのラインアンドスペスで第１及び第２
の電極３．７を形成すると５ｍｍ’のチップ内に、１２
．５Ｘ１０’ ｂｉｔと非常に大きな記憶容量を持つ、
また、本発明の記憶装置自体を形成するに必要なフォト
工程は２回と短く、また同一基板上にロウデコーダ、カ
ラムデコーダ、センスアンプ、Ｉ１０ゲートが通常の半
導体プロセスを用いて形成されるため、小さく、高性能
で低コストの記憶装置である。As shown in FIGS. 2(a) and 2(b), the storage capacity of the storage device of the present invention is 1 μm line and space.
When electrodes 3.7 are formed, 12
．． It has a very large storage capacity of 5 x 10' bits.
In addition, the photo process required to form the memory device itself of the present invention is as short as two, and the row decoder, column decoder, sense amplifier, and I10 gate are formed on the same substrate using a normal semiconductor process. , a small, high-performance, low-cost storage device.
また、センスアンプなどの集積回路に用いられるフィー
ルド酸化膜形成工程を用いて第１の絶縁層２を形成して
も良い。Alternatively, the first insulating layer 2 may be formed using a field oxide film forming process used in integrated circuits such as sense amplifiers.
［発明の効果］ 本発明の効果を以下に説明する。[Effect of the invention] The effects of the present invention will be explained below.
（１）本発明の記憶装置は非常に大きな記憶容量を持つ
。(1) The storage device of the present invention has a very large storage capacity.
（２）本発明の記憶装置のビット単価は安い。(2) The bit unit cost of the storage device of the present invention is low.
第１図（ａ）、（ｂ）は本発明の記憶装置の上視図、断
面図、第２図（ａ）、（ｂ）は本発明の記・旧装置をマ
トリクス状に配置した記憶装置の上視図、断面図である
。
１・・・半導体基板
２・・・第１の絶縁層
３・・・第１の電極
４・・・半導体層
５・・・第２の絶縁層
６・・・第３の絶縁層
７・・・第２の電極FIGS. 1(a) and (b) are top views and cross-sectional views of a storage device of the present invention, and FIGS. 2(a) and (b) are storage devices in which old and new devices of the present invention are arranged in a matrix. They are a top view and a cross-sectional view. 1... Semiconductor substrate 2... First insulating layer 3... First electrode 4... Semiconductor layer 5... Second insulating layer 6... Third insulating layer 7...・Second electrode
Claims (1)
上に形成された第１の電極、前記第１の電極上に形成さ
れた半導体層、前記半導体層上に形成された第２の絶縁
層、前記第２の絶縁層上に形成された第３の絶縁層、前
記第３の絶縁層上に形成された第２の電極を具備したこ
とを特徴とする記憶装置。A first insulating layer formed on a semiconductor substrate, a first electrode formed on the insulating layer, a semiconductor layer formed on the first electrode, and a second insulating layer formed on the semiconductor layer. A memory device comprising an insulating layer, a third insulating layer formed on the second insulating layer, and a second electrode formed on the third insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63222614A JPH0271564A (en) | 1988-09-06 | 1988-09-06 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63222614A JPH0271564A (en) | 1988-09-06 | 1988-09-06 | Memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0271564A true JPH0271564A (en) | 1990-03-12 |
Family
ID=16785216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63222614A Pending JPH0271564A (en) | 1988-09-06 | 1988-09-06 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0271564A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004507091A (en) * | 2000-08-14 | 2004-03-04 | マトリックス セミコンダクター インコーポレーテッド | Highly integrated arrays and charge storage devices, and methods of making them |
-
1988
- 1988-09-06 JP JP63222614A patent/JPH0271564A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004507091A (en) * | 2000-08-14 | 2004-03-04 | マトリックス セミコンダクター インコーポレーテッド | Highly integrated arrays and charge storage devices, and methods of making them |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2817500B2 (en) | Nonvolatile semiconductor memory device | |
| US9502133B2 (en) | Semiconductor device | |
| JP5019436B2 (en) | Semiconductor integrated circuit | |
| KR101932909B1 (en) | Semiconductor memory device and semiconductor device | |
| US20080061298A1 (en) | Semiconductor element and semiconductor memory device using the same | |
| JP6034980B2 (en) | Semiconductor device | |
| TW201225080A (en) | Semiconductor memory device and method for driving the same | |
| US6597031B2 (en) | Ovonic unified memory device and magnetic random access memory device | |
| JP3039245B2 (en) | Semiconductor memory device | |
| JPH0621478A (en) | Thin film semiconductor device | |
| JPH0271564A (en) | Memory device | |
| JP2588311B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| JPS5856981B2 (en) | Programmable read-only semiconductor memory circuit device | |
| JPS6343901B2 (en) | ||
| JPH0786532A (en) | Semiconductor device and its manufacture | |
| JPS60189253A (en) | Static semiconductor memory device | |
| JPS6197961A (en) | Semiconductor integrated device | |
| JPS63182859A (en) | Semiconductor integrated circuit device | |
| JPH04144282A (en) | Semiconductor device | |
| JPS6083366A (en) | Semiconductor memory device | |
| JPS6379369A (en) | Semiconductor storage device | |
| JPH0936335A (en) | Nonvolatile semiconductor storage device | |
| JPH09134974A (en) | Ferroelectric memory device | |
| JPH0382074A (en) | Semiconductor device | |
| JPS6224663A (en) | Semiconductor memory device |