JPS5856981B2 - Programmable read-only semiconductor memory circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable read-only semiconductor memory circuit device using a programmable read-only semiconductor memory element.

Programmable read-only semiconductor memory elements (hereinafter referred to as programmable memory elements for simplicity) have conventionally been
A device having the following configuration as shown in the figure has been proposed.

That is, for example, it has a single crystal semiconductor substrate 3 having a structure in which an N type single crystal semiconductor layer 2 is formed by epitaxial growth on a P type single crystal semiconductor substrate 1, and within the semiconductor layer 2, the main surface is formed. A P-type single crystal semiconductor region 6 is formed from the 4 side to form a PN junction 5.

On the other hand, another PN junction 7 is inserted into the region 6 from the main surface 4 side.
An N-type single crystal semiconductor region 8 is formed so as to form an N-type single crystal semiconductor region 8.

Further, a conductive layer 9 made of, for example, aluminum is formed on the main surface 4 of the semiconductor layer 2 of the substrate 30 and is connected to the region 8 . A magnetic layer 10 (not shown) is formed.

Note that 11 is an N-type buried region, 12 is a P-type semiconductor region for isolation between elements, and 13 is an insulating layer.

The above is the configuration of a conventionally proposed programmable memory element.

According to such a configuration, P is present between the conductive layers 9 and 10.
Unless a voltage higher than the breakdown voltage of the N-junction 7 is applied, the area between the conductive layers 9 and 10 exhibits a high resistance state, for example, "1" on a binary display. If a voltage higher than the breakdown voltage of the PN junction is applied between layers 9 and 10, semiconductor layer 2, regions 6 and 8, and conductive layers 9 and 1
Current flows through 0, which generates heat at the location of the PN junction 7, melts the conductive layer 9, and the molten metal enters the regions 6 and 8 and within 8,
A region is formed of a eutectic alloy of a metal made up of molten metal and a semiconductor made up of regions 6 and 8,
Therefore, the area between the conductive layers 9 and 10 is programmed to be in a low resistance state as "0" in binary representation.

However, in the case of such a programmable memory element, programming is performed only after the regions 6 and 8 are formed of a eutectic alloy, and for this purpose, the semiconductor layer 2, the regions 6 and 8, It is necessary that the current flowing through the conductive layers 9 and 10 be sufficiently large.

Therefore, the above-mentioned conventional programmable memory element requires a large current for its programming, and since the semiconductor layer 2 is connected to the semiconductor body 1, P
This has the disadvantage that the heat generated at the N-junction 7 is likely to be dissipated into the semiconductor substrate 1.

Furthermore, a programmable memory element shown in FIG. 2 and having the following configuration has also been proposed.

That is, for example, the single crystal semiconductor substrate 23 has a structure in which an N type single crystal semiconductor layer 22 is formed by epitaxial growth on a P type single crystal semiconductor substrate 21, and within the semiconductor layer 22, the main surface 24 is formed. From the side, PN junction 25
A P-type single crystal semiconductor region 26 is formed to form a P-type single crystal semiconductor region 26.

Further, a conductive layer 27 (not shown) connected to the semiconductor layer 22 is formed on the main surface 24 of the semiconductor layer 22 of the substrate 230, and a polycrystalline semiconductor layer 29 is formed through the insulating layer 28.
The semiconductor region 2 is further arranged through the insulating layer 28.
6 and one end of the semiconductor layer 29, a conductive layer 30 is formed extending therebetween;
A conductive layer 31 is formed which extends and connects to the other end of the semiconductor layer 29 via the conductive layer 8 .

Note that 32 indicates an N-type buried region, and 33 indicates a P-type semiconductor region for isolation between elements.

The above are the configurations of other conventionally proposed programmable storage elements.

According to such a configuration, the diode D includes the semiconductor layer 22 and the semiconductor region 26.

In addition, a polycrystalline semiconductor layer 29 and conductive layers 30 and 31
through the conductive layers 30 and 31, the semiconductor layer 2
Unless a sufficient current is passed to generate enough heat to melt the conductive layers 29 and 30, the conductive layers 29 and 30 exhibit a low resistance state, for example, as "0" on a binary display. In such a state, if a large enough current is passed through the conductive layers 30 and 31 to the polycrystalline semiconductor layer 29 to generate enough heat to melt the semiconductor layer 29, the polycrystalline semiconductor layer 29 will melt. Layer 29 melts and conductive layer 30
and 31 constitutes a programmable memory element main body E which is programmed to a high resistance state as "1" in binary display and is connected in series with a diode D.

However, in the case of such a programmable memory element, it is programmed only by blowing out the polycrystalline semiconductor layer 29, and for this purpose, the current flowing through the polycrystalline semiconductor layer 29 via the diode D is not sufficiently large. need something.

Therefore, the conventional programmable memory element shown in FIG. 2 also had the disadvantage of requiring a large current for programming, as in the case of FIG. 1.

Therefore, the present invention proposes a new programmable read-only semiconductor memory circuit device using a new programmable memory element that does not have the above-mentioned drawbacks, and will become clear from the detailed description below.

FIG. 3 shows an example of a programmable memory element that can be applied to the programmable read-only semiconductor memory circuit device (hereinafter referred to as a programmable memory circuit for simplicity) according to the present invention, and has the configuration described below.

That is, for example, a single crystal semiconductor substrate 31 made of silicon
An insulating layer 32 made of, for example, silicon oxide and having a low thermal conductivity (actually, such an insulating layer 32 is formed by thermal oxidation treatment on the main surface of the single crystal semiconductor substrate 31) is formed thereon. The substrate 33 has a configuration that is similar to that shown in FIG.

However, on the main surface 34 of the insulating layer 32 of the substrate 33,
For example, an N-type polycrystalline or amorphous semiconductor region 35 made of, for example, silicon, and a P-type polycrystalline or amorphous semiconductor region made of silicon, which is connected to the region 35 to form a PN junction 36. A semiconductor region 37 and an N-type polycrystalline or amorphous semiconductor region 39, which is also made of silicon and is connected to the region 37 on the opposite side from the region 35 so as to form another PN junction 3B. They are arranged side by side.

In practice, regions 35, 37 and 39 are formed by depositing an undoped semiconductor layer on the insulating layer 32 of the substrate 33 by vapor phase growth, and then depositing an undoped semiconductor layer within the semiconductor layer. The region 37 is formed by performing an ion implantation process of P-type impurity and N-type impurity, and the region 37 is formed by ion implantation process of boron, for example, from 10" to 1013a.
As having an impurity concentration of tom/cd,
The regions 35 and 39 are formed to have a high impurity concentration of 1020 to 1102 ato/cd by, for example, arsenic ion implantation.

Further, on the main surface 34 of the insulating layer 32 of the substrate 33, an insulating layer 40 made of, for example, silicon oxide and having a low thermal conductivity is arranged to cover the regions 35, 37 and 39.

This insulating layer 40 is formed by a so-called CVD method.

On the other hand, a window 41 in the insulating layer 40 allows the region 35 to be exposed to the outside.
and a window 42 that exposes the region 39 to the outside.A conductive layer made of, for example, aluminum is formed on the insulating layer 40 and is connected to the regions 35 and 39 through windows 41 and 42, respectively. sexual layers 43 and 44 are formed.

The above is an example of the structure of a programmable memory element that can be applied to the programmable memory circuit according to the present invention. According to the structure of such a programmable memory element, it has the structure of a two-terminal N0PN0 type semiconductor element as a whole. Therefore, when looking between the conductive layers 43 and 44, the fourth
As shown by the curve 45 in the figure, when the voltage V between the conductive layers 43 and 44 is gradually increased, the L junctions 36 and 38 are not destroyed until the value reaches VB, so a high resistance characteristic of 100 or more is exhibited. When VB is reached, one of the junctions 36 and 38 biased in the opposite direction by the voltage V, for example junction 36, breaks down and exhibits a voltage V vs. current I characteristic with a negative resistance characteristic, so that the region 35, 37, and 39 and conductive layers 43 and 44, heat is generated at the junction 36, and the impurities contained in the region 35 at a high concentration are removed. Area 3
7 and then reaches region 39, resulting in junction 36
and 38 were both destroyed,
It exhibits the voltage V vs. electric construction characteristics as shown by the curve 46 in FIG.

Therefore, unless the voltage ■ is applied between the conductive layers 43 and 44 at a value equal to or higher than the value VB, the conductive layers 43 and 44 will exhibit a high resistance state as, for example, "1" in binary display. However, from this state, if a voltage of VB or more is applied between the conductive layers 43 and 44, the voltage between the conductive layers 43 and 44 becomes 2 as shown by the curve 46 in FIG. The value display is programmed to a low resistance state, for example as "0".

According to the programmable memory element applicable to the programmable memory circuit according to the present invention shown in FIG. 3, the programmable memory element exhibits a function as a programmable memory element.

By the way, the program is obtained by breaking the junctions 36 and 38, and by applying a voltage that can destroy the junction 36 (or 38), the junction 36 (or 38) is destroyed. , thereby forming regions 35, 37 and 39, and conductive layers 43 and 44.
Current flows through junction 36 (or 38
), and as a result, the region 35 (or 3
9) is introduced into region 37 and then reaches region 35 (or 39).

Therefore, even though programming requires a current to flow through regions 35, 37 and 39 and conductive layers 43 and 44, that current is Compared to this, it is much smaller and better.

This means that regions 35, 37 and 39 are
and 44 are connected, the insulation layers 32 and 4 are connected.
Therefore, the heat generated at the junction 36 (or 38) is not dissipated to the outside unnecessarily, and the heat generated at the junction 36 (or 38) is not unnecessarily dissipated to the outside, and the heat generated at the junction 36 (or 38) does not enter the region 37 from the region 35 (or 39). This is even more so because the impurity diffusion that then reaches region 39 (or 35) is easy because regions 35, 37, and 39 are polycrystalline or amorphous.

Therefore, the programmable memory element applicable to the programmable memory circuit according to the present invention described above has the great feature that programming can be obtained with a small current.

In the above description, an example of a programmable memory element has been described in which the regions 35, 37, and 39 are arranged side by side on the main surface 34 of the insulating layer 32 of the substrate 33.

However, as shown in FIG. 5, corresponding parts to those in FIG. A programmable storage element that can be applied to the programmable storage circuit according to the present invention has the same configuration as that shown in FIG. 4, except that these layers are sequentially stacked on the main surface 34 of the layer 32. Other examples are also possible.

Further, as shown in FIG. 6, corresponding parts to those in FIG. 5 are given the same reference numerals and detailed explanations are omitted.
5 and 37 are stacked in that order on the main surface 34 of the insulating layer 32, and the conductive layer 43 is connected to the region 37. The configuration
Still other examples of programmable storage elements that can be applied to the programmable storage circuit according to the present invention are also possible.

Further, although not shown, the structure described above in FIG. 3 is similar to that of FIG. 3 except that region 39 is omitted and, however, conductive layer 43 is connected to region 37. can also be used as yet another example of a programmable storage element that can be applied to the programmable storage circuit according to the present invention.

Furthermore, the configuration in which the above-mentioned "N-type" is read as "P-type" and "P-type" is read as "N-type" may be considered as another example of a programmable memory element that can be applied to the programmable memory circuit according to the present invention. You can also.

The programmable memory element applicable to the programmable memory circuit according to the present invention has been clarified above. Next, the programmable memory circuit according to the present invention using the above-mentioned programmable memory element will be described.

FIG. 7 shows an example of a programmable memory circuit according to the present invention, and has the configuration described below.

That is, it has a P-type single-crystal semiconductor substrate 51 made of silicon, for example, and N-type single-crystal semiconductor regions 53 and 54 are formed in the substrate 51 from its main surface 52 side.

Further, a relatively thick thermal layer made of silicon oxide, for example, formed by thermal oxidation treatment on the main surface 52 of the substrate 51, extending so as to surround the regions 53 and 54, is formed on the main surface 52 of the substrate 51, for example. An insulating layer 55 with low conductivity is formed.

Furthermore, a conductive layer 57 made of, for example, polycrystalline silicon imparted with conductivity is formed on the main surface 52 of the substrate 51 between the regions 53 and 54 with a relatively thin insulating layer 56 interposed therebetween.

Furthermore, on the main surface 52 of the substrate 51, an N-type material similar to the region 35 of the programmable memory element described above in FIG. A polycrystalline or amorphous semiconductor region 58 is formed.

Further, the region 58 and the region 58 are connected and extended on the side opposite to the region 54 so as to form a PN junction 59 corresponding to the PN junction 36 in FIG. 3, similar to the region 37 in FIG. 3. P of
A type polycrystalline to amorphous semiconductor region 60 is formed.

Additionally, region 60 extends in conjunction with region 39 of FIG. 3, opposite region 58, to form a PN junction 61, which corresponds to PN junction 38 of FIG. A similar N-type polycrystalline or amorphous semiconductor region 62 is formed.

Further, on the substrate 51, an insulating layer 63 having a low thermal conductivity similar to the insulating layer 40 in FIG.
7, and regions 58, 60 and 62.

On the other hand, windows 64 and 65 are formed in the insulating layer 63 to expose the region 53 and the region 62 to the outside, respectively.
Conductive layers 66 and 67 are formed on insulating layer 63 and extend through windows 64 and 65 to connect to regions 53 and 62, respectively.

The above is an example of the configuration of the programmable memory circuit device according to the present invention.

According to such a configuration, the substrate 51, the regions 53 and 54
, an insulating layer 56 and a conductive layer 57 define regions 53 and 54 as source (or drain) regions and drain (or source) regions, respectively, a region between regions 53 and 54 of substrate 51 as a channel region, and insulating layer 56 as a channel region. MIS in which the gate insulating layer and the conductive layer 57 are used as the gate electrode 5T
A field effect transistor is formed.

Furthermore, since areas 58, 60 and 62 are similar to areas 35, 37 and 39 of the programmable storage element in FIG. 3, they constitute a programmable storage element Q similar to the programmable storage element in FIG. ing.

Further, a region 53 serving as a MIS field effect transistor source (or drain) region is formed in the conductive layer 66.
In addition, the area 5 configuring the programmable memory element Q
8 is connected to the region 54 serving as the drain (or source) region of the transistor T, and the region 62 is connected to the conductive layer 67, so that the transistor T and the storage element Q are connected in series between the conductive layers 66 and 67. It is connected to the.

Therefore, the conductive layer 57 (
When a required voltage is applied to the conductive layer 6 (gate electrode), an N-type channel is formed between the regions 53 and 54 of the substrate 51, and the regions 53 and 54 become electrically conductive.
6 is connected to the region 58 constituting the storage element Q through the transistor T, and the storage element Q has been selected.

Furthermore, when the memory element Q is in the selected state, the memory element Q is moved between the conductive layers 66 and 67, as in the case of the memory element described above in FIG. 3, although detailed explanation is omitted. conductive layers 66 and 67 unless a voltage having a value greater than or equal to the value corresponding to the value VB described above in FIG. 3 is applied.
For example, a high resistance state is indicated as "1" in the binary display between the two, but from this state, the conductive layers 66 and 67
During this time, applying a voltage having a value greater than or equal to the value corresponding to the value VB programs conductive layers 66 and 67 to a low resistance state.

Therefore, the programmable memory circuit according to the present invention shown in FIG. 1 exhibits a function as a programmable memory circuit device that is programmed in the manner that the memory element Q is programmed.

Since the program is performed using a memory element Q similar to the programmable memory element shown in FIG.
It has the feature that the programming can be performed with a small current.

Further, it is said that such a characteristic function as a programmable memory circuit device can be obtained by a series circuit of one MIS field effect transistor and one programmable memory element Q similar to the programmable memory element described above in FIG. It has the feature that it can be obtained with a simple configuration.

Further, the programmable memory circuit according to the present invention shown in FIG. 7 is a combination of an MIS field transistor T and a programmable memory element Q, and the programmable memory element Q is composed of a polycrystalline or amorphous semiconductor, M
Both the IS field effect transistor and the programmable memory element Q have a configuration in which they are made of polycrystalline or amorphous semiconductors.

Therefore, the MIS field effect transistor T itself can be easily manufactured in a highly densely integrated configuration compared to a bipolar transistor, and the programmable memory element Q itself can be made of polycrystalline or amorphous semiconductor. Moreover, since the MIS field effect transistor and the programmable memory element Q are composed of the same polycrystalline or amorphous negative semiconductor, they can be easily manufactured using a common polycrystalline semiconductor. It can be easily manufactured from an amorphous semiconductor layer.

Further, although the MIS field effect transistor T itself can only handle a small current compared to a bipolar transistor, since the programmable memory element Q is composed of a polycrystalline or amorphous semiconductor, it can be programmed with a small current, and therefore, By combining it with the MIS field effect transistor programmable memory element Q, the function as a programmable memory circuit can be achieved with a small current.

Therefore, in combination with the MIS field effect transistor programmable memory element Q, it is possible to achieve the effect of being able to program with a small current and easily manufacturing with high density. Has characteristics.

Incidentally, it is also possible to use a configuration in which MIS field effect transistors are replaced with bipolar transistors, but in this case, the use of bipolar transistors itself
Compared to the case of using MIS field effect transistors, it cannot be said that it is easier to manufacture with high density integration.
In addition, a part of the bipolar transistor cannot be made of the same material as the programmable memory element, such as the MIS field effect transistor according to the present invention being made of the same polycrystalline or amorphous semiconductor as the programmable memory element. Therefore, it cannot be said that a programmable memory circuit can be manufactured easily.

In the case of the embodiment of the programmable memory circuit according to the present invention shown in FIG. 7, the series circuit with the MIS field effect transistor programmable memory element Q is
It has a feature that it can be obtained with an extremely simple structure, in that the region 5B forming the structure is configured in such a manner that it also serves as a conductive layer for forming a series circuit.

Furthermore, in the above, the programmable storage element Q is
An example of a programmable storage circuit according to the present invention has been described in the case of a programmable storage element similar to that described above in FIG.

However, although a detailed description of the drawings will be omitted, in the configuration described above in FIG. 7, the storage element Q is replaced with a programmable storage element similar to that described in FIG. A configuration similar to that shown in FIG. 7 can also be used as another example of the programmable storage circuit according to the present invention.

Furthermore, in the configuration described above in FIG.
Yet another example of a programmable storage circuit according to the present invention is similar to that of FIG. 7, except that region 62 is omitted, but a conductive layer 67 is coupled to region 60. You can also do that.

Various other modifications and changes may be made without departing from the spirit of the invention.

Thus, the programmable storage circuit according to the present invention has been clarified.

Next, a programmable successive memory circuit device using the programmable memory circuit will be described.

FIG. 8 shows an example of this, and has the configuration described below.

That is, a plurality of n row selection lines X1. X2...
...Xn, and a plurality of m column selection lines Y1. Y2...
...It has Ym.

Therefore, the row selection line Xi (i=1, 2...
...n) and column selection line Yj (j=1,2...--
. . m), an example of the programmable memory circuit according to the present invention described above in FIG. 5T is connected to column selection line Yj.

Moreover, programmable memory circuits M11 to M1m.

The conductive layers 66 of pigeon□~M2m...--Mn1~Mnm are connected to a power supply terminal 81 common to them.

Furthermore, one end of the row selection line Xi is connected to a power supply terminal (ground) paired with the power supply terminal 81 through an MIS field effect transistor H1 whose gate is connected to the programming row selection signal terminal AXi.

Further, one end of the row selection line Xi is connected to a detection circuit K common to the transistors Gi-Gn through an MIS field effect transistor Gi connected to a gate read row selection signal terminal BXi.

The above is an example of the configuration of a programmable read-only memory circuit device using a programmable memory circuit according to the present invention.

According to such a configuration, although a detailed explanation is omitted, a sufficient voltage is applied to the power supply terminal 81 so that the programmable memory circuit Mij is programmed as described above in FIG.
In addition, a column selection line Yj and a row selection signal terminal A for programming
MI of the programmable memory circuit Mij in Xi, respectively.
If a voltage sufficient to turn on the S field effect transistor T and the MIS field effect Hi is applied, the programmable memory circuit Mij is programmed.

In addition, while the programmable memory circuit Mij is programmed in this way, a voltage at which the programmable memory circuit Mij is not programmed is applied to the power supply terminal 81, and the column selection line Yj and the read voice row selection signal terminal B
If sufficient voltage is applied to A current flows through the transistor Gi and reaches the detection circuit K.
For example, it is detected as "1" in the value display, and the detection output is obtained at the output terminal U derived by the circuit, so that the information of "1" in the binary display is stored in the programmable storage circuit Mij. is read out.

However, even if the same voltages as at the time of reading described above are applied to the power supply terminal 81 and the selection lines Yj and BXi in a state where the programmable memory circuit Mij is not programmed,
Since the programmable memory circuit Mij is not programmed, no current flows through the programmable memory circuit Mij and the transistor Gi to the detection circuit K, and this causes the detection circuit to display "0" in the binary display. is detected, and its detection output is obtained at output terminal U.

Therefore, according to the programmable read-only memory circuit device shown in FIG. 8, the function as a programmable read-only memory circuit device is obtained, and the programmable memory circuit Mij used therein is the programmable memory circuit according to the present invention. Therefore, it has great features such as being able to function as a programmable read-only memory circuit device with a small current.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views showing conventional programmable read-only semiconductor memory elements, respectively. FIG. 3 is a cross-sectional view showing an example of a programmable read-only semiconductor memory element that can be applied to the programmable read-only semiconductor memory circuit device according to the present invention. FIG. 4 is a curve diagram showing the voltage-current characteristics. 5 and 6 are cross-sectional views showing other examples of programmable read-only semiconductor memory elements that can be applied to the programmable read-only semiconductor memory circuit device according to the present invention, respectively. FIG. 7 is a cross-sectional view showing an example of a programmable read-only semiconductor memory circuit device according to the present invention using a programmable read-only semiconductor memory element. FIG. 8 is a system diagram showing an example of a programmable read-only semiconductor memory circuit device using the programmable read-only semiconductor memory circuit device according to the present invention. 31... Single crystal semiconductor gas, 32...-...
Insulating layer, 33...Substrate, 34.52...
・Main surface, 35.37°39.5B, 60,62...
...Polycrystalline to amorphous semiconductor region, 36.38.59.
61...PN junction, 40.55, 56, 63.
...--Insulating layer, 43,44°5? , 66.67...
--- Conductive layer, 51 --- Single crystal semiconductor substrate, 53.54 --- Single crystal semiconductor region, T ---
...MIS field effect transistor, Q...--Programmable read-only semiconductor memory element.

Claims (1)

[Claims] 1. A first semiconductor substrate having a first conductivity type opposite to the second conductivity type, which is formed from the main surface side in a single crystal semiconductor substrate having a second conductivity type. a second single-crystal semiconductor region; a conductive layer disposed on the main surface of the single-crystal semiconductor substrate, on a region between the first and second single-crystal semiconductor regions, with a first insulating layer interposed therebetween; the first layer, which is disposed on the main surface of the single crystal substrate via a second insulating layer with low thermal conductivity, and is connected to the second single crystal semiconductor region.
a first polycrystalline or amorphous semiconductor region having a conductivity type, and a first polycrystalline or amorphous semiconductor region connected to the first polycrystalline or amorphous semiconductor region to form a PN junction, and having a second conductivity type. the single crystal semiconductor substrate, the first and second single crystal semiconductor regions, the first insulating layer, and the conductive layer; A MIS field effect transistor is configured, including the first and second polycrystalline or amorphous semiconductor regions, and between the first and second polycrystalline or amorphous semiconductor regions;
Unless a voltage that can destroy the PN junction is applied, the region between the first and second polycrystalline or amorphous semiconductor regions exhibits a high resistance state as "1" (or "O") on a binary display. However, from this state, if a voltage capable of destroying the PN junction is applied between the first and second polycrystalline or amorphous semiconductor regions, the first and second polycrystalline or amorphous semiconductor regions A programmable read-only semiconductor memory element is configured in which a region between the quality semiconductor regions is programmed to a low resistance state as "0" (or "1") in binary display, and is connected in series with the MIS field effect transistor. A programmable read-only semiconductor memory circuit device.