JPH0621478A - Thin film semiconductor device - Google Patents

Abstract

PURPOSE:To realize a semiconductor device which has a greater storage capacity and is easy to fabricate, and is further likely to electrically write/erase data. CONSTITUTION:A control gate 22 and a floating gate 25 are insulated with an insulating film 24 and are laminated on the upper portion of an insulating substrate 24, and a semiconductor film 26 is provided through the insulating film 24 on which a thin film section is formed, facing the floating gate 5. There are further provided a drain electrode 30 electrically connected with the semiconductor film 26 and including a protrusion 30a facing the floating gate 25 through the thin film section, and a source electrode 29 electrically connected with the semiconductor film 26 and formed at a predetermined interval from the drain electrode 30.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film semiconductor device, and more particularly to a thin film semiconductor device having a floating gate and capable of storing data.

[0002]

2. Description of the Related Art A fixed memory device (Read Only Memory) is used as a main memory of a computer, and a floating gate type memory element which is electrically erasable and rewritable in the fixed memory device. EEPROM
(Electrically Erasable Prog-ramable ROM) is known.

FIG. 2 shows a field effect type (MOSFET type) EEP having a floating gate formed on a silicon substrate.
It is a sectional view of one memory element of ROM. This storage element
A storage transistor 11 and a selection transistor 12 are formed in a pair.

In FIG. 2, a first diffusion region 2'containing a high concentration of impurities near the surface of the silicon substrate 1 and a second diffusion region 2'having a conductivity opposite to the conductivity of the silicon substrate 1 and a second diffusion region 2 '.
Diffusion regions 3'are formed apart from each other by a predetermined distance (a distance required to form a channel). Further, a third diffusion region 4'is formed near the surface of the silicon substrate 1 at a predetermined distance from the first diffusion region 2 '. An insulating film made of silicon oxide (SiO ₂ ) or the like is formed on the surface of the silicon substrate 1 on which the first diffusion region 2 ′, the second diffusion region 3 ′, and the third diffusion region 4 ′ are formed. 5
Are formed.

First diffusion region 2'and second diffusion region 3 '
A floating gate 6 is provided above the channel portion of the storage transistor 11 and the first diffusion region 2 ′ so as to face each other with an insulating film 5 in between, and above the floating gate 6 with the insulating film 5 in between. A control gate 7 is provided. Further, the gate electrode 8 of the selection transistor, which is opposed to the channel portion of the selection transistor between the first diffusion region 2'and the third diffusion region 3 ', with the insulating film 5 interposed therebetween, is provided. .

The portion of the floating gate 6 facing the first diffusion region 2'is formed close to the first diffusion region 2 ', and that portion of the floating gate 6 and the first diffusion region 2'are formed. The insulating film 5 sandwiched between is thinly formed, and the thin portion of the insulating film 5 forms the tunnel region 9. Further, a bit line 10 made of a metal such as aluminum (outer 1) is formed on the insulating film 5, and the bit

[0007]

[Outer 1]

The line 10 is connected to the third diffusion region 4 '. In the above structure, the first diffusion region 2 ', the second diffusion region 3', the insulating film 5, the floating gate 6, and the control gate 7 form a memory transistor 11.
By accumulating charges in the floating gate 6, binary data of "0" and "1" is stored. Further, the third diffusion region 4, the first diffusion region 2 ′, the insulating film 5 and the gate electrode 8 form a selection transistor 12 having a MOSFET structure. By turning on the selection transistor 12, the storage transistor Data writing / reading to / from 11 is performed. Here, the first diffusion region 2 ′ and the second diffusion region 3 ′ are the drain region 2 and the source region 3 of the memory transistor 11, respectively. The third diffusion region is the drain region 4 of the selection transistor 12, and the first diffusion region 2'is the selection transistor 1
It is also the source area of 2. In the following description, the first diffusion region 2'is simply called the drain region 2.

The MOSFET type EEPROM configured as described above is well known, but its operation will be briefly described. First, at the time of writing, a predetermined voltage is applied to the gate electrode 8 to turn on the selection transistor 12. After that, a predetermined voltage is applied to the control gate 7, the bit line 10 and the silicon substrate 1. As a result, the pn junction between the drain region 2 and the silicon substrate 1 is strongly reverse-biased, and the charges generated by the avalanche effect are injected into the floating gate 6 through the tunnel region 9 by tunneling, and the floating gate 6 is charged. Accumulated. Since the floating gate 6 is surrounded by the insulating film 5, the electrons accumulated in the floating gate 6 are retained even after the voltage is not applied to the drain electrode 2 and the control gate 5, and the storage transistor 11 is turned on. Keep doing

On the other hand, at the time of reading, the bit line 10 is connected to the ground or a positive voltage V _DD and a predetermined voltage is applied to the gate electrode 9 to turn on the selection transistor 10. Then, the output level of the source region 3 is checked to detect whether the storage transistor is on or off.

When erasing data, predetermined voltages having different polarities are applied to the drain region 2 and the control gate 5, and the charges accumulated in the floating gate 6 are tunneled through the tunnel region 9. And is discharged to the drain region 2.

As described above, it is possible to electrically store and erase charges in the floating gate 6, and to store binary data "0" and "1" depending on the presence / absence of charges in the floating gate. ing.

[0013]

2. Description of the Related Art The floating gate type memory element using the conventional MOSFET described above is formed on a silicon single crystal substrate. This silicon single crystal substrate always has a defect in its crystal structure, and the probability of existence of this defect is significantly increased as the chip area increases. Therefore, conventionally, in order to increase the storage capacity, increasing the chip size significantly increases the failure rate.
The elements have been miniaturized. However, due to the miniaturization of the device, problems in the device structure, high precision patterning,
There is a problem in the manufacturing process such that complicated process control is required.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a thin film semiconductor element in which stored contents can be electrically written, has a large storage capacity, and is easy to manufacture.

[0015]

In order to achieve the above object, the present invention has a structure in which a control gate and a floating gate are insulated and laminated by an insulating film above an insulating substrate, and the floating film is formed through an insulating film having a thin film portion formed thereon. A semiconductor film is provided facing the gate, is electrically connected to the semiconductor film, and is electrically connected to the semiconductor film and a first electrode having a protrusion that faces the floating gate through the thin film portion. It is characterized in that it is provided with a first electrode and a second electrode that are connected to each other and are formed at a predetermined interval.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a floating gate type storage element made of a thin film semiconductor according to an embodiment of the present invention.

In the figure, a control gate 22 of a storage transistor 40 and a gate electrode 23 of a selection transistor are provided on an insulating substrate 21 at a predetermined distance. An insulating film 24 is formed on the insulating substrate 21 on which the control gate 22 and the gate electrode 23 are formed, and a floating gate 25 surrounded by the insulating film 24 is provided above the control gate 22. There is. Further, semiconductor films 26 and 27 made of intrinsic amorphous silicon are formed on the insulating film 24 above the floating gate 25 and above the gate electrode 23, respectively. , And the contact layer 28 for ohmic contact on the semiconductor film 27 for the select transistor 50 except the portions of the channel regions 26a, 27a of the transistors 40, 50.
Is provided. A metal electrode is provided in contact with the contact layer 28, and the metal electrode integrally connects the source electrode 29 of the memory transistor, the drain electrode 30 of the memory transistor 40 and the source electrode 31 of the selection transistor 50. The connection electrode 32 and the drain electrode 33 of the selection transistor are formed. A protrusion 30 a is formed on a part of the drain electrode 30 of the memory transistor 40 so as to penetrate the contact layer 28 and the semiconductor film 26 and protrude toward the floating gate 25. The protrusion 30 a is provided between the protrusion 30 a and the floating gate 25. Insulating film 24
Has a thickness that is thin enough to allow tunneling and forms a tunnel region 33. Control gate 2
2, the thin film transistor including the floating gate 25, the semiconductor film 26, the contact layer 28, the source electrode 29, and the drain electrode 30 constitutes a storage transistor 40 that holds electric charge in the floating gate 25, and the gate electrode 23 and the insulating film 24. The inverted stagger type thin film transistor including the semiconductor film 27, the contact layer 28, the source electrode 31, and the drain electrode 33 constitutes a selection transistor 50 for controlling writing / reading of data, and serves as a drain electrode of the storage transistor 40. The source electrode of the selection transistor 50 is electrically connected by the connection electrode 32.

In the above structure, a glass substrate or the like can be used as the insulating substrate 21, and the control gate 22,
For the gate electrode 23 and the floating gate 25, chromium (Cr), molybdenum (Mo), tungsten (W) are used.
And the like. For the metal electrodes forming the source electrodes 29, 31, the drain electrodes 30, 33, the connection electrodes 32, etc. of each transistor, a metal having a low electric resistance such as aluminum (outer 2) is used.

[0019]

[Outside 2]

It is possible to: Further, as the insulating film 24, silicon nitride (SiN), silicon dioxide (Si)
O ₂ ) and the like are used for the semiconductor films 26 and 27, intrinsic amorphous silicon or polycrystalline silicon, and n-type amorphous silicon or the like having a high impurity concentration is used for the contact layer 29.

Next, the operation of this embodiment configured as described above will be described. The selection transistor 50 is a well-known T
By controlling the voltage applied to the second gate electrode 23 which is FT, conduction (ON) / interruption (OFF) can be controlled.

The writing of data (accumulation of charges in the floating gate 25) and the reading of data (detection of the presence of charges accumulated in the floating gate 25) are performed with the selection transistor 50 turned on.

First, when writing data,
The selection transistor 50 is turned on, and high voltages having different polarities are applied to the drain electrode 33 of the selection transistor 50 and the control gate 22 of the storage transistor 40. A high voltage is applied between the drain electrode 30 of the storage transistor 40 and the control gate 22 via the selection transistor 50, and the electric field between the protrusion 30a of the drain electrode 30 and the control gate 22 becomes extremely high. Since the tunnel region 34 made of the insulating film 24 interposed therebetween has an extremely thin thickness, a tunnel current flows from the protrusion 30a of the drain electrode 30 to the floating gate 25, and charges are accumulated in the floating gate 25. Since the floating gate 25 is surrounded by the insulating film 24, even if the voltage is not applied between the drain electrode 30 and the control gate 22, the electric charge accumulated in the floating gate 25 is retained without being discharged. When electric charges are accumulated in the floating gate 25, the resistance between the drain electrode 30 and the source electrode 29 of the storage transistor 40 in which the electric charges are accumulated becomes low resistance (ON). On the other hand, when electric charges are not accumulated in the floating gate 25, the resistance between the drain electrode 30 and the source electrode 29 of the storage transistor 40 becomes high resistance (OFF).

As described above, the memory element of this embodiment has the drain electrode 30 and the source electrode 29 of the memory transistor 40.
Binary data of "1" and "0" can be stored depending on whether the resistance between them is low resistance (ON) or high resistance (OFF).

Next, the data is read out first by using the memory
The source electrode 29 of the transistor 40 is grounded or predetermined.
Voltage V_DDConnect to and then select as in writing
The transistor 50 is turned on and output to the drain electrode 30.
Voltage is ground or V _DDTo detect
Done by. That is, the memory transistor 40 is turned on.
If the voltage is on, the voltage applied to the source electrode 29 is selected.
Output to the drain electrode 33 via the transistor 50 for
To be done.

When erasing data, the selection transistor 50 is turned on, and the voltage applied to the control gate 22 and the floating gate 25 has the opposite polarity to the voltage applied at the time of writing data to cause floating. The charges accumulated in the gate 25 are released into the insulating film 24.

As described above, by controlling the voltage of the drain electrode 30 applied via the control gate 22 and the selecting transistor 50 and controlling the on / off of the selecting transistor 50, the charge to the floating gate 25 of the memory transistor 40 is changed. Accumulation / release can be performed, and binary data can be stored depending on the on / off state of the storage transistor 40.

When the floating gate type storage element of this embodiment is used in an EEPROM, the selection transistor 5 is used.
The drain electrode 33 of 0 is connected to the bit line and the gate electrode 23 is connected to the word line for use. Then, the floating gate type storage element is placed on the insulating substrate 21.
They are arranged in a matrix of rows and n columns, and these selection transistor gate electrodes 23 are connected to m bit lines in each row, and the drain electrodes 33 are connected to n word lines in each column. By doing so, an EEPROM of m bits × n words can be realized.

As described above, in this embodiment, a large number of transistors are arrayed on a large substrate by using a thin film forming technique capable of forming a uniform thin film on a large area. In addition, a storage element having a large storage capacity can be manufactured without requiring complicated process control. Also, the memory transistor 40
Since metal such as chromium (Cr) and aluminum (outer 3) can be used for the wiring lines such as the control gate 22 of the above, a diffusion layer or polysilicon is used for the wiring lines.

[0030]

[Outside 3]

The wiring resistance can be remarkably reduced as compared with the conventional MOSFET floating gate type storage element. Further, since the insulating film 24, the semiconductor film 26, and the contact layer 28 can be continuously formed by a plasma CVD method or the like, the number of mobile ions and fixed charges contained in the insulating film 24 can be reduced, and the film quality of each layer can be reduced. Is improved and the interface characteristics between the insulating film 24 and the semiconductor film 26 are improved, so that the electrical characteristics of the storage transistor 40 and the selection transistor 50 are stabilized. Further, since the semiconductor films of the respective transistors 40 and 50 are formed in the form of independent islands patterned by the photolithography method, they are insulated by doping impurities and / or increasing the film thickness like a conventional MOSFET type memory element. The isolation of the channel region of each transistor is more complete than the isolation of the device by forming a film.

In this embodiment, the selection transistor 50 is used.
Although the selection transistor 50 is not provided, the voltage may be directly applied to the drain electrode 30.

Further, in this embodiment, the memory transistor 4 is used.
Although 0 is an inverse stagger type TFT, the TFT used for the memory transistor is not limited to the inverse stagger type and may be a stagger type, a coplanar type, or an inverse coplanar type.

[0034]

As described above, according to the present invention, since the floating gate type memory element is constituted by the thin film transistor, a large number of transistors can be arrayed and formed on the insulating substrate having a large area, and the manufacturing process is also possible. Since each transistor is formed by a thin film forming technique whose process control is simple, a storage element which is easy to manufacture and has a large storage capacity can be obtained.

[Brief description of drawings]

FIG. 1 is a floating gate type storage element according to an embodiment of the present invention.

FIG. 2 is a conventional floating gate memory element using a MOSFET.

[Description of Reference Signs] 21 Insulating Substrate 22 Control Gate 24 Insulating Film 25 Floating Gate 26 Semiconductor Film 29 Source Electrode 30 Drain Electrode 30a Projection 33 Tunnel Region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (1)

[Claims] 1. An insulative substrate, a control gate formed on the insulative substrate, a floating gate formed in a laminated manner to insulate the control gate, and an insulating surrounding the floating gate. An insulating film having a thin film portion, a semiconductor film formed to face at least the floating gate, and a protrusion electrically connected to the semiconductor film and facing the floating gate via the thin film portion of the insulating film. A thin film semiconductor device comprising: a first electrode having a portion formed therein; and a second electrode electrically connected to the semiconductor film and formed at a predetermined distance from the first electrode.