JPH0936335A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of high speed writing and erasing with high reliability, without increasing a chip area. SOLUTION: A plurality of memory cell transistors MC00 -MCnm are arranged in the parts where bit lines BL0-BLn intersect word lines WL0 -WLm . A plurality of selection transistors Qsd0-Qsdn for writing are connected with the bit lines BL0-BLn. A selection transistor Qss for erasing is connected with the source side of the memory cell transistor MCco -MCnm . A constant voltage power supply PS is connected with the selection transistor Qsd0-Qsdn for writing and the selection transistor Qss for erasing, via load resistors RD and RS. The yield voltage Vz of the selection transistors Qsd0-Qsdn for writing and the selection transistor Qss for erasing is set lower than the yield voltage Vd of the memory cell transistors MC00 -MCnm .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device.

[0002]

2. Description of the Related Art In a non-volatile semiconductor memory device, a voltage is applied to a source / drain impurity diffusion region (source / drain region) of a memory cell during a write operation and an erase operation.

The higher the voltage applied between the source / drain region and the silicon substrate, the faster the write and erase operations of the memory cell. However, when the voltage applied between the source / drain region and the silicon substrate exceeds the breakdown voltage between the source / drain region and the silicon substrate, hot carriers generated in the channel region of the memory cell destroy the memory cell. .

Therefore, in order to realize high-speed writing and erasing operations with high reliability of the non-volatile semiconductor memory device, the voltage applied between the source / drain region and the silicon substrate is the source / drain region. It is desirable to maintain a voltage slightly lower than the breakdown voltage between the silicon substrate and the substrate.

Conventionally, in order to keep the voltage applied between the source / drain region and the silicon substrate constant,
It is common practice to install a stabilizing circuit. For example, as disclosed in Japanese Patent Application Laid-Open No. 62-1194, the voltage is maintained to a level high enough to perform writing / erasing satisfactorily and low enough not to damage the memory cell transistor. It is disclosed to provide a stabilizing circuit. The conventional voltage stabilizing circuit is provided in the peripheral portion other than the cell region on the memory chip, between the constant voltage source and the select transistor connected to the source side and the drain side of the memory cell transistor.

[0006]

However, since the voltage stabilizing circuit is provided in the peripheral portion other than the cell region on the memory chip, the chip area increases. The increase in chip area goes against the demand for higher integration and smaller size of the nonvolatile semiconductor memory device.

The present invention provides a non-volatile semiconductor memory device capable of high-speed and highly reliable writing and erasing operations without increasing the chip area.

[0008]

According to the present invention, firstly, a plurality of bit lines, a plurality of word lines arranged to intersect the bit lines, and driven by the word lines to selectively output data. A plurality of memory cell transistors for storing data and exchanging data with the bit line, and the bit line for selectively applying a voltage for writing data to the memory cell transistor. A plurality of write select transistors each connected to
An erase select transistor connected to the memory cell for applying a voltage for collectively erasing the data stored in the memory cell transistor, and a voltage to the write select transistor and the erase select transistor. A non-volatile semiconductor memory device comprising: a constant voltage source for supplying a voltage to a memory cell, the breakdown voltage between a source region and a drain region of the write select transistor and the erase select transistor, and a substrate. Provided is a nonvolatile semiconductor memory device characterized by being set to be lower than a breakdown voltage between a source region and a drain region of a cell transistor and a substrate.

Secondly, according to the present invention, a plurality of bit lines, a plurality of word lines crossing the bit lines, and word lines driven by the word lines to selectively store data are provided. A plurality of memory cell transistors for exchanging data with a bit line, and a plurality of memory cell transistors connected to the bit lines for selectively applying a voltage for writing data to the memory cell transistors. Write select transistor, an erase select transistor connected to the memory cell for applying a voltage for collectively erasing data stored in the memory cell transistor, the write select transistor, and A non-volatile semiconductor memory device comprising: a constant voltage source for supplying a voltage to the erase selection transistor, comprising: A memory cell transistor, a drain region and a source region formed on a main surface of a semiconductor substrate at predetermined intervals, a first insulating film formed on the surface of the semiconductor substrate, the drain region, and the source region; Of the floating gate conductor layer disposed on the first insulating film, the control gate conductor layer disposed on the floating gate conductor layer so as to face each other with the second insulating film interposed therebetween, and the drain region and the source region. At least two, which are provided in contact with a part of the semiconductor substrate, have the same conductivity type as the semiconductor substrate, have a higher impurity concentration than the semiconductor substrate, and form a PN junction between the drain region and the source region; Provided is a non-volatile semiconductor memory device including two high-concentration impurity diffusion layers.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. According to a first aspect of the present invention, a breakdown voltage between a source region and a drain region of a write select transistor and an erase select transistor of a nonvolatile semiconductor memory device and a substrate is calculated. It is characterized in that it is set lower than the breakdown voltage between and.

FIG. 1 is a circuit diagram showing one mode of the nonvolatile semiconductor memory device of the first invention of the present application. BL ₀ ~ in the figure
BL _n indicates a plurality of bit lines, respectively. Bit line BL
_A plurality of word lines WL _{0 to} WL _m are arranged so as to intersect with _{0 to} BL _n . Bit lines BL _{0 to} BL _n and word line W
Word lines WL _{0 to} W are provided at the intersections of L _{0 to} WL _m.
A plurality of memory cell transistors MC _{00 to} MC _nm for driving the L _m to selectively store the data and exchanging the data with the bit line BL are arranged. In addition, each bit line BL ₁ to BL _n, a plurality of write select transistor Qsd ₀ ~Qsd _n for selectively applying the voltage for writing data to the memory cell transistors MC ₀₀ to MC _nm is respectively It is connected.

[0012] on the source side of the memory cell transistor MC ₀₀ ~MC _nm is, MC ₀₀ ~MC in the memory cell transistor
An erase selection transistor Qss for applying a voltage for collectively erasing the data stored in _nm is connected.

Further, a write selection transistor Qsd.
₀ ～Qsd The _n and erasing selection transistors Qss, respectively, load resistors RD and via the RS constant voltage source P
S is connected.

Non-volatile semiconductor memory device 1 as described above
0, write select transistors Qsd _{0 to} Qs
The breakdown voltage Vz between the sd _n and source and drain regions of the erasing selection transistors Qss and the substrate,
The breakdown voltage Vd between the source region and drain region of the memory cell transistors MC _{00 to} MC _nm and the substrate is set lower than the breakdown voltage Vd.

Write selection transistors Qsd _{0 to} Qs
As a means to lower the breakdown voltage Vz of the sd _n and erasing selection transistors Qss, for example, it can be applied as follows means.

First, as shown in FIG. 2, the selection transistor 20 is a field oxide film 22 formed in a predetermined region of a P-type well 21 formed on the main surface of a silicon substrate.
, A source region 23 and a drain region 24 formed apart from each other in an element formation region defined by the field oxide film 22, and a gate oxide film 25 on the channel region between the source region 23 and the drain region 24. When the P-type well 21 below the field oxide film 22 is doped with P-type impurities to form the P-type high-concentration impurity diffusion layer 27, the P-type high-concentration impurity diffusion layer 27 is formed. The breakdown voltage Vz can be reduced by increasing the amount of P-type impurities injected into the high-concentration impurity diffusion layer 27.

As shown in FIG. 3, the source region 23,
Below the channel region 28 and the drain region 29,
When a P-type high-concentration impurity diffusion layer (punch through stop) 30 for preventing punch through is formed,
The breakdown voltage Vz can be lowered by increasing the amount of P-type impurities injected into the punch-through stop 30.

Further, as shown in FIG. 4, the selection transistor 20 includes a field oxide film 22 formed in a predetermined region of a P-type well 21 formed on the main surface of a silicon substrate.
A source region 23 and a drain region 24, which are formed apart from each other in an element formation region defined by the field oxide film 22, and a source region 23 and a drain region 2.
When the gate electrode 26 formed via the gate oxide film 25 is provided on the channel region between 4 and 4, the breakdown voltage Vz is lowered by increasing the implantation amount of the P-type impurity in the P-type well 21. be able to.

Further, as shown in FIG. 5, the interlayer insulating film 3
P-type impurities are injected through the contact hole 32 formed in 1 to form a P-type high-concentration impurity diffusion layer 33,
The breakdown voltage Vz can be lowered by increasing the implantation amount of the P-type impurity in the P-type high-concentration impurity diffusion layer 33. In addition to the means described above, the method of controlling the breakdown voltage Vz that is usually performed in a semiconductor device can be applied to the nonvolatile semiconductor memory device of the present invention.

The memory cell transistors MC _{00 to} MC _nm of the non-volatile semiconductor memory device 10 of the present invention may have any memory cell transistor structure of a general non-volatile semiconductor memory device. That is, for example, EPRO
M (erasable programmable ROM), EEPROM (elect
It may be a memory cell transistor used in a nonvolatile semiconductor memory device such as a flash erasable programmable ROM) or a flash EEPROM. More specifically, FLOTOX (floating gate
tunnel oxide) structure, offset gate structure or ET
A memory cell transistor having an OX (stack type) structure can be used.

The nonvolatile semiconductor memory device 10 according to the first invention of the present application as described above has the memory cell transistor MC _00.
To MC _nm choice for writing connected to the drain region or the source region transistor Qsd ₀ ~Qsd _n and breakdown voltage Vz of the erasing selection transistors Qss is, the source region or the drain region of the memory cell transistors MC ₀₀ to MC _nm and the substrate Is set lower than the breakdown voltage (Vb). Therefore, the memory cell transistor M
The voltages Vd and Vs for the write or erase operation supplied to the memory cell transistors MC _{00 to} MC _nm during the data write or erase operation to C _{00 to} MC _nm are the load resistances RD and RS and the write selection. Transistor Qs
The d ₀ ~Qsd _n and voltage stabilizing circuit formed by the breakdown diode parasitic on the erasing selection transistors Qss, select transistors Qsd write
_{0 ~Qsd n} and breakdown voltage of the erasing selection transistors Qss Vz and equal. As a result, the voltages Vd and Vs supplied to the memory cell transistors MC _{00 to} MC _nm are
Breakdown voltage Vb of memory cell transistors MC _{00 to} MC _nm
Is always lower than the memory cell transistors MC _{00 to} M
It is possible to prevent a breakdown phenomenon from occurring between the C _nm drain region or source region and the substrate.

The write operation and erase operation in the non-volatile semiconductor memory device 20 will be described more specifically below. Write operation When data is written only to an arbitrary memory cell transistor (for example, MC ₂₁ ), the supply voltage Vg ₁ = Vpp to the word line WL ₁ , the write select transistor Qsd ₂
= ON, supply voltage to another word line WL Vg ₀ = Vg ₁
= ... Vg _m = GND, other selection transistor Qsd
₀ = Qsd ₁ = ... Qsd _n = OFF is set, the erasing selection transistor Qss is set to 0N, and it is connected to GND. At this time, the voltage stabilizing circuit formed by the load resistance RD and the breakdown diode parasitic on the write selection transistor Qsd ₂ causes the drain side of the memory cell transistor MC ₂₁ from the constant voltage source PS via the selection transistor Qsd _2. To the select transistor Qsd ₂ becomes equal to the breakdown voltage Vz of the select transistor Qsd ₂ . As a result, the voltage Vd supplied to the memory cell transistor MC ₂₁ is the breakdown voltage V of the memory cell transistors MC ₂₁
Since it is always lower than b, the memory cell transistor MC ₂₁
It is possible to prevent the breakdown phenomenon from occurring between the drain region or the source region of the substrate and the substrate.

Erase Operation When erasing the data stored in all the memory cell transistors MC _{00 to} MC _nm , the supply voltage Vg ₀ = Vg ₁ = Vg ₂ = ... Vg _m = to all the word lines WL -10
V to GND, all selection transistors Qsd ₀ = Qsd
₁ = Qsd ₂ = ... Qsd _n = OFF, the erasing selection transistor Qss = ON, and the constant voltage source PS and the load resistor RS are connected. At this time, the voltage stabilizing circuit formed by the load resistance RS and the breakdown diode parasitic on the erasing selection transistor Qss causes the memory cell transistor MC from the constant voltage source PS via the load resistance RS and the erasing selection transistor Qss. _The voltage Vs supplied to the source side of _{00 to} MC _nm becomes equal to the breakdown voltage Vz of the selection transistor Qss. As a result, the voltage Vs supplied to the memory cell transistors MC ₀₀ to MC _nm, the memory cell transistors MC ₀₀ ~M
Since it is always lower than the breakdown voltage Vb of C _nm , it is possible to prevent the breakdown phenomenon from occurring between the drain region or the source region of the memory cell transistors MC _{00 to} MC _nm and the substrate.

As described above, according to the nonvolatile semiconductor memory device 10 of the first invention of the present application, the voltages Vd and Vs for writing and erasing the memory cell transistors MC _{00 to} MC _nm are written / erased. It can be maintained at a value high enough to be satisfactorily performed and low enough not to cause destruction of the memory cell transistor. Therefore, high-speed write and erase operations can be realized with high reliability. That is, the memory cell transistors MC _{00 to} MC _nm
Stable writing and erasing operations are performed even when the voltages Vd and Vs for writing and erasing data to and from the memory cell are set to values higher than the voltage applied to the source region and the drain region during the read operation of the memory cell. Is possible.

Further, the voltage stabilizing circuit for stabilizing the voltage Vd, the Vs, and a load resistor RD or RS, a breakdown diode parasitic on the write select transistor Qsd ₀ ~Qsd _n or erasing selection transistors Qss Is formed by. As a result, the area of the entire device can be reduced (about 51%) compared to the case where the voltage stabilizing circuit is formed in the peripheral portion other than the memory cell region.

Next, a nonvolatile semiconductor memory device according to the second invention of the present application will be described. A second invention of the present application is a non-volatile semiconductor memory device, wherein a memory cell transistor has a drain region and a source region formed on a main surface of a semiconductor substrate at predetermined intervals, a semiconductor substrate, a drain region and a source. A first insulating film formed over the surface of the region, a floating gate conductor layer arranged on the first insulating film, and a control gate conductor arranged oppositely on the floating gate conductor layer via a second insulating film. Provided in contact with the layer and a part of the drain region and the source region, has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, and has a PN junction between the drain region and the source region, respectively. It is characterized by comprising at least two high-concentration impurity diffusion layers for forming.

FIG. 6 is a circuit diagram showing one mode of the nonvolatile semiconductor memory device of the second invention of the present application. BL _{0 in the} figure
To BL _n respectively show, a plurality of bit lines. Bit line B
A plurality of word lines WL _{0 to} WL _m intersecting with L _{0 to} BL _n
Is wired. The portion of the bit lines BL ₀ to BL _n and word line WL ₀ to WL _m intersect the word lines WL ₀ ~
A plurality of memory cell transistors MC _{00 to} MC _nm for driving the WL _m to selectively store data and exchanging data with the bit line BL are respectively arranged. In addition, each bit line BL ₁ to BL _n, a plurality of write select transistor Qsd ₀ ~Qsd _n for selectively applying the voltage for writing data to the memory cell transistors MC ₀₀ to MC _nm is respectively It is connected.

[0028] on the source side of the memory cell transistor MC ₀₀ ~MC _nm is, MC ₀₀ ~MC in the memory cell transistor
An erase selection transistor Qss for applying a voltage for collectively erasing the data stored in _nm is connected.

Further, the write select transistor Qsd.
₀ ~ Qsd to _n and the erasing selection transistors Qss, respectively, load resistors RD and via the RS constant voltage source P
S is connected.

Nonvolatile semiconductor memory device 6 as described above
In 0, in the memory cell transistor MC ₀₀ ~MC in _nm of the memory cell, the memory cell transistor MC ₀₀ ~MC
_One breakdown diode D _{oo to} D _nm is formed on the source side and the drain side of _nm .

FIG. 7 shows an example of the memory cell transistors MC _{00 to} MC _nm of the non-volatile semiconductor memory device 60. In the figure, 71 is a P-type silicon substrate. Silicon substrate 7
A source region 72 and a drain region 73 are formed on the main surface of No. 1 at intervals. Source area 7
A floating gate 76 is formed above the channel region 74 defined by 2 and the drain region 73 with the first gate oxide film 75 interposed therebetween. A control gate 78 is formed above the control gate 76 via a second gate oxide film 77. An interlayer insulating film 79 is formed on the surface of the silicon substrate 71 including the first gate oxide film 75, the floating gate 76, the second gate oxide film 77, and the control gate 78.

A high-concentration impurity in which a source region 72 and a drain region 73 of the silicon substrate 71 are in contact with a part of the same conductivity type as the silicon substrate 71, that is, a P-type impurity is injected at a higher concentration than the silicon substrate. Diffusion layer 80,
81 is formed.

In the memory cell transistor MC _xy described above, the N-type source region 72 and drain region 73 and P
A breakthrough diode D _xy is formed by the PN junction between the high-concentration impurity diffusion layers 80 and 81 of the shape. The breakdown voltage Vz of the breaking diode is lower than the breakdown voltage Vb between the source region 72 and the drain region 73 of the memory cell transistor MC _xy and the silicon substrate 71. Therefore, the memory cell transistor MC ₀₀
The voltage Vd, Vs for the write or erase operation supplied to the memory cell transistors MC ₀₀ -MC _nm at the time of the data write operation or the erase operation of the data to the MC _nm is the load resistances RD, RS and the breakdown diode D _xy . Due to the voltage stabilizing circuit formed in step _S1 , the breakdown voltage becomes equal to the breakdown voltage Vz of the breakdown diode Dxy. As a result, the voltage V supplied to the memory cell transistors MC _{00 to} MC _nm
Since d and Vs are always lower than the breakdown voltage Vb of the breakdown diode D _xy , the memory cell transistor MC ₀₀
It is possible to prevent the breakdown phenomenon from occurring between the drain region or the source region of .about.MC _nm and the substrate.

The region where the high-concentration impurity diffusion layers 80 and 81 are formed is not particularly limited as long as it is other than the channel region, but is a breakthrough diode D _xy formed by a PN junction between the source region 72 and the drain region. When the breakdown occurs, the hot region does not deteriorate the first gate oxide film 75 and the channel region 74.
The write operation and the erase operation in the nonvolatile semiconductor memory device 60 will be described more specifically below. Write operation When data is written only to an arbitrary memory cell transistor (for example, MC ₂₁ ), the supply voltage Vg ₁ = Vpp to the word line WL ₁ , the write select transistor Qsd ₂
= ON, supply voltage to another word line WL Vg ₀ = Vg ₁
= ... Vgm = GND, other selection transistor Qsd
₀ = Qsd ₁ = ... Qsd _n = OFF is set, the erasing selection transistor Qss is set to 0N, and it is connected to GND. At this time, the load resistor RD and the breakdown diode D ₂₁ formed in the memory cell transistor MC ₂₁ .
Due to the voltage stabilization circuit formed by, the voltage Vd supplied from the constant voltage source PS to the drain side of the memory cell transistor MC ₂₁ becomes equal to the breakdown voltage Vz of the breakdown diode D ₂₁ . As a result, the voltage Vd supplied to the memory cell transistors MC _21, because always lower than the breakdown voltage Vb of the memory cell transistors MC _21, breakdown between the drain region or the source region and the substrate of the memory cell transistors MC ₂₁ phenomena Can be prevented.

Erase Operation When erasing the data stored in all the memory cell transistors MC _{00 to} MC _nm , the supply voltage Vg ₀ = Vg ₁ = Vg ₂ = ... Vgm = − to all the word lines WL. 10
V to GND, all selection transistors Qsd ₀ = Qsd
₁ = Qsd ₂ = ... Qsd _n = OFF, the erasing selection transistor Qss = ON, and the constant voltage source PS and the load resistor RS are connected. At this time, the voltage stabilizing circuit formed by the load resistance RS and the breakdown diode D ₂₁ provided in the memory cell transistors MC _{00 to} MC _nm causes the constant voltage source PS to change the load resistance R from the constant voltage source PS.
The voltage Vs supplied to the source side of the memory cell transistors MC _{00 to} MC _nm via S and the erase selection transistor Qss is the breakdown voltage Vs of the selection transistor Qsd _2.
is equal to z. As a result, the memory cell transistor M
Since the voltage Vs supplied to C _{00 to} MC _nm is always lower than the breakdown voltage Vb of the breakdown diode D ₂₁ , the breakdown phenomenon occurs between the drain region or source region of the memory cell transistors MC _{00 to} MC _nm and the substrate. Can be prevented. That is, the memory cell transistors MC ₀₀ to
Voltages Vd and Vs for writing and erasing to MC _nm
Even when is set to a value higher than the voltage applied to the source region and the drain region during the read operation of the memory cell, stable write and erase operations can be performed.

Next, referring to FIGS.
An example of a method of manufacturing the memory cell transistor MC _xy in the nonvolatile semiconductor memory device 60 of the invention will be described.

As shown in FIG. 8, boron (B) as a P-type impurity is formed on the main surface of the silicon substrate 81 (resistivity 10 Ω · cm) by a first thermal oxide film having a film thickness of 100 Å (A). A gate oxide film 82 is formed.

Next, on the surface of the first gate oxide film 82,
A first polysilicon layer 83 having a film thickness of 1000 A is deposited by the low pressure CVD method. The first polysilicon layer 83 is
Resistivity 0.01Ω ・ cm, Sheet resistance 1000Ω / Squa
re.

Then, a second gate oxide film 84 having a three-layer structure is formed on the surface of the first polysilicon layer 83.
The second gate oxide film 84 has a film thickness of 60 by the low pressure CVD method.
A first layer made of a silicon oxide film of A, a second layer made of a silicon nitride film having a film thickness of 160 A by the low pressure CVD method, and a third layer made of a silicon oxide film having a film thickness of 60 A formed by the low pressure CVD method.

Then, a 2000 A thick second polysilicon layer 85 is deposited on the surface of the second gate oxide film 84 by a low pressure CVD method. This second polysilicon layer 85
Has a resistivity of 0.001Ω · cm and a sheet resistance of 50Ω / Sq.
uare.

The first gate oxide film 82, the first polysilicon layer 83, and the second gate oxide film 84 laminated as described above.
Then, the second polysilicon layer 85 is formed on the gate region 8 as shown in FIG. 9 according to a normal photolithography technique.
Patterning is performed, leaving only 6. In this patterning, when the first polysilicon layer 83 is etched, the etching selection ratio between the first gate oxide film 82 and the first polysilicon layer 83 is set to 10: 1 or more, and the etching is performed by the first gate oxide film 82. Stops when about 50% has been scraped.

Next, the entire silicon substrate 81 is thermally oxidized in an oxygen atmosphere at 850 ° C. for 60 minutes, and as shown in FIG. 10, the silicon substrate 81, the side wall surface of the first polysilicon layer 83, and the second polysilicon. A silicon oxide film 87 is formed on the side wall surface and the surface of the layer 85. In this case, the silicon oxide film 87 is formed on the surface of the silicon substrate 81 with a film thickness of 100A. Next, arsenic (As) is implanted as an N-type impurity toward the main surface of the silicon substrate 81. Arsenic is 6
3.0 × 10 ¹⁵ cm ⁻³ by implantation energy of 0 KeV
Inject at the concentration of. Then, the silicon substrate 81 is 850
Anneal at 60 ° C. for 60 minutes. As a result, the silicon substrate 8
A source region 88 and a drain region 89 are formed at 1.

Next, as shown in FIG. 11, the gate region 86 and the source region 8 are formed on the surface of the silicon substrate 81.
8 and a portion of the drain region 89, a photoresist layer 90 is formed. This photoresist layer 90
The film thickness above the second polysilicon layer 85 is about 0.5 μm. Next, boron (B) is implanted into the main surface of the silicon substrate 81 at a concentration of 3.0 × 10 ¹⁴ cm ⁻³ with an implantation energy of 125 KeV. After that, the silicon substrate 81 is annealed at 850 ° C. for 60 minutes. As a result, as shown in FIG.
1, a P-type high concentration impurity diffusion region 91 is formed.

13 and 14 _show a modification of the method of manufacturing the memory cell transistor MC _xy in the nonvolatile semiconductor memory device 60 of the second invention. FIG. 10 described above.
Source region 88 and drain region 8 described with reference to
Up to the step of forming 9, the same procedure as the above method is performed. After depositing a silicon oxide film for a gate spacer with a film thickness of 3000 A on the surface of the silicon oxide film 87 on the surface of the silicon substrate 81 by a low pressure CVD method,
Anisotropic etching is performed to form the gate spacer 101 as shown in FIG. In this anisotropic etching, the selection ratio of the silicon oxide film for the gate spacer and the silicon substrate 81 is set to 10: 1 or more, and the etching is stopped when the silicon oxide film 87 is scraped by about 30%. .

Next, boron (B) is added to the silicon substrate 81 by implantation energy of 125 KeV to 3.0.
^{Implant at} a concentration of × 10 ¹⁴ cm ^-3 . After that, the silicon substrate 81 is annealed at 850 ° C. for 60 minutes in an oxygen atmosphere. As a result, as shown in FIG.
1, a P-type high concentration impurity diffusion region 102 is formed in a self-aligned manner. At the same time, the silicon substrate 81 and the second
Silicon oxide film 103 is formed on the surface of polysilicon layer 85. The film thickness of the silicon oxide film 103 formed on the surface of the silicon substrate 81 is 100A.

Further, FIGS. 15 and 14 describe another modification of the method of manufacturing the memory cell transistor MC _xy in the nonvolatile semiconductor memory device 60 of the second invention.
Up to the step of forming the source region 88 and the drain region 89 described with reference to FIG. 10 above, the same procedure as the above method is performed. An interlayer insulating film 111 is formed on the surface of the silicon oxide film 87 on the surface of the silicon substrate 81. The interlayer insulating film 111 has a two-layer structure, and is composed of a first layer made of a non-doped silicon oxide film having a film thickness of 1000 A by a plasma CVD method and a second layer made of a BPSG film having a film thickness of 5000 A by a plasma CVD method. .

Next, the interlayer insulating film 111 and the silicon oxide film 87 in the source region 88 and the drain region 89.
Are formed by the normal photolithography technique. The diameter of the contact holes 112, 113 is 0.8
μm.

After that, boron (B) is added to the silicon substrate 81 by an implantation energy of 125 KeV to 3.0.
^{Implant at} a concentration of × 10 ¹⁴ cm ^-3 . After that, the silicon substrate 81 is annealed at 850 ° C. for 60 minutes. As a result, as shown in FIG. 16, the P-type high concentration impurity diffusion region 114 is formed in the silicon substrate 81 in a self-aligned manner. The contact holes 112 and 113 are formed on the upper metal wiring layer (not shown), the source region 88 and the drain region 89.
Used to connect and respectively.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an aspect of a nonvolatile semiconductor memory device of a first invention of the present application.

FIG. 2 is a cross-sectional view showing an example of a method of controlling the breakdown voltage Vz in the select transistor of the nonvolatile semiconductor memory device of the first invention of the present application.

FIG. 3 is a cross-sectional view showing an example of a method of controlling the breakdown voltage Vz in the select transistor of the nonvolatile semiconductor memory device of the first invention of the present application.

FIG. 4 is a cross-sectional view showing an example of a method of controlling the breakdown voltage Vz in the select transistor of the nonvolatile semiconductor memory device of the first invention of the present application.

FIG. 5 is a cross-sectional view showing an example of a method of controlling the breakdown voltage Vz in the select transistor of the nonvolatile semiconductor memory device of the first invention of the present application.

FIG. 6 is a circuit diagram showing an aspect of a nonvolatile semiconductor memory device of a second invention of the present application.

FIG. 7 is a sectional view showing an example of a memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 8 is a sectional view showing a step of an example of a method of manufacturing the memory cell transistor of the nonvolatile semiconductor memory device according to the second invention of the present application.

FIG. 9 is a cross-sectional view showing a step in an example of a method of manufacturing a memory cell transistor of a nonvolatile semiconductor memory device according to the second invention of the present application.

FIG. 10 is a cross-sectional view showing a step of an example of a method of manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 11 is a cross-sectional view showing a step of an example of a method of manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 12 is a sectional view showing a step of an example of a method of manufacturing the memory cell transistor of the nonvolatile semiconductor memory device according to the second invention of the present application.

FIG. 13 is a cross-sectional view showing a step of a modification of the method for manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 14 is a cross-sectional view showing a step of a modification of the method for manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 15 is a cross-sectional view showing a step of another modification of the method for manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

FIG. 16 is a cross-sectional view showing a step of another modification of the method for manufacturing the memory cell transistor of the nonvolatile semiconductor memory device of the second invention of the present application.

[Explanation of symbols]

10, 60 ... Nonvolatile semiconductor memory device, BL ... Bit line, WL ... Word line, MC ... Memory cell transistor,
Qsd ... write selection transistor, Qss ... erase selection transistor, RD, RS ... load resistance, PS ... low voltage source.

Claims (3)

[Claims] 1. A plurality of bit lines, a plurality of word lines arranged to intersect with the bit lines, and a plurality of word lines driven by the word lines to selectively store data. A plurality of memory cell transistors for exchanging data, and a plurality of write selection transistors each connected to the bit line for selectively applying a voltage for writing data to the memory cell transistors An erase select transistor connected to the memory cell for applying a voltage for collectively erasing the data stored in the memory cell transistor, and the write select transistor and the erase select transistor. A non-volatile semiconductor memory device comprising a constant voltage source for supplying a voltage, comprising: A breakdown voltage between a source region and a drain region of the transistor and the erasing select transistor and the substrate is set lower than a breakdown voltage between the source region and the drain region of the memory cell transistor and the substrate. Non-volatile semiconductor memory device. 2. A plurality of bit lines, a plurality of word lines arranged to intersect with the bit lines, and a plurality of word lines driven by the word lines to selectively store data and to and from the bit lines. A plurality of memory cell transistors for exchanging data, and a plurality of write selection transistors each connected to the bit line for selectively applying a voltage for writing data to the memory cell transistors An erase select transistor connected to the memory cell for applying a voltage for collectively erasing the data stored in the memory cell transistor, and the write select transistor and the erase select transistor. A non-volatile semiconductor memory device comprising a constant voltage source for supplying a voltage, comprising: A drain region and a source region formed on the main surface of the semiconductor substrate at a predetermined distance from each other, a first insulating film formed on the surface of the semiconductor substrate and the drain region and the source region, and the first insulating film. A floating gate conductor layer disposed on the insulating film, a control gate conductor layer disposed on the floating gate conductor layer so as to face the second insulating film, and a part of the drain region and the source region. Is provided in contact with the semiconductor substrate, has the same conductivity type as the semiconductor substrate, and has a higher impurity concentration than the semiconductor substrate,
A non-volatile semiconductor memory device comprising at least two high-concentration impurity diffusion layers each forming a PN junction between the drain region and the source region. 3. The high-concentration impurity diffusion layer causes hot carriers to pass through the first insulating film when a breakdown occurs at a PN junction formed between the drain region and the source region and the high-concentration impurity diffusion layer. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed in a region far from the channel region so as not to deteriorate.