JPH0270438U - - Google Patents

Info

Publication number
JPH0270438U
JPH0270438U JP15026488U JP15026488U JPH0270438U JP H0270438 U JPH0270438 U JP H0270438U JP 15026488 U JP15026488 U JP 15026488U JP 15026488 U JP15026488 U JP 15026488U JP H0270438 U JPH0270438 U JP H0270438U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
semiconductor device
circuit board
conductive sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15026488U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15026488U priority Critical patent/JPH0270438U/ja
Publication of JPH0270438U publication Critical patent/JPH0270438U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の混成集積回路を示す断面図、
第２図は本実施例で用いる導電性シートを示す斜
視図、第３図は他の実施例を示す断面図、第４図
、第５図、及び第６図は従来例を示す断面図であ
る。 １……混成集積回路基板、３……導電性シート
、４……半導体装置、５……挾持クリツプ。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 複数の半導体素子が混成集積回路基板上に
    固着された混成集積回路において、 前記混成集積回路基板の一側辺周端部に弾性力
    を有する導電性シートを介して樹脂封止された半
    導体装置が載置され、前記半導体装置と前記混成
    集積回路基板とが挾持クリツプで挾持されてなる
    ことを特徴とする混成集積回路。 (2) 前記半導体装置は書き込み、消去可能なＲ
    ＯＭからなることを特徴とする請求項１記載の混
    成集積回路。 (3) 前記導電性シートは絶縁性シートで形成さ
    れ、その両面から多数の線状導体が突出されてい
    ることを特徴とする請求項１記載の混成集積回路
    。 (4) 前記混成集積回路基板の両面周端部に前記
    導電性シートを介して前記半導体装置が配置され
    、前記挾持クリツプで前記両面に配置された前記
    半導体装置を挾持することを特徴とする請求項１
    記載の混成集積回路。 (5) 前記混成集積回路基板は絶縁処理された金
    属基板であることを特徴とする請求項１記載の混
    成集積回路。
JP15026488U 1988-11-17 1988-11-17 Pending JPH0270438U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15026488U JPH0270438U (ja) 1988-11-17 1988-11-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15026488U JPH0270438U (ja) 1988-11-17 1988-11-17

Publications (1)

Publication Number Publication Date
JPH0270438U true JPH0270438U (ja) 1990-05-29

Family

ID=31423253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15026488U Pending JPH0270438U (ja) 1988-11-17 1988-11-17

Country Status (1)

Country Link
JP (1) JPH0270438U (ja)

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