JPH0269972A - Semiconductor integrated device - Google Patents
Semiconductor integrated deviceInfo
- Publication number
- JPH0269972A JPH0269972A JP63221925A JP22192588A JPH0269972A JP H0269972 A JPH0269972 A JP H0269972A JP 63221925 A JP63221925 A JP 63221925A JP 22192588 A JP22192588 A JP 22192588A JP H0269972 A JPH0269972 A JP H0269972A
- Authority
- JP
- Japan
- Prior art keywords
- elements
- same
- dummy
- circuit
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 102220016912 rs111033279 Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は高精度のアナログ回路を有する半導体集積装置
上の素子の配置方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of arranging elements on a semiconductor integrated device having a highly accurate analog circuit.
[従来の技術]
D/A変換回路、A/D変換回路等アナログ回路の中で
オペアンプと抵抗素子・容量素子等のイこの時入力イン
ピーダンス43 (Z、)や帰還インピーダンス44
(Z2)は抵抗素子・容量素子などが用いられるが例え
ば抵抗素子を用いて3倍の増幅回路を構成する場合、
Z2=R
Z、=R/3 (3本並列に接続する)として全く同
一構造の抵抗素子4本を用意する。[Prior art] In analog circuits such as D/A conversion circuits and A/D conversion circuits, input impedance 43 (Z, ) and feedback impedance 44 of operational amplifiers, resistive elements, capacitive elements, etc.
For (Z2), a resistive element, a capacitive element, etc. are used, but for example, when constructing a triple amplifier circuit using a resistive element, Z2 = R Z, = R / 3 (3 connected in parallel), which is exactly the same. Prepare four resistive elements of the structure.
半導体集積回路上に実現する場合、ある基本長の抵抗素
子に対し%の長さの抵抗素子を用いて、抵抗値を%にそ
ろえることは難しい。そこで第2図の様に同一構造で同
一間隔で同一方向に配置された素子を並列接続すること
によって正確な抵抗比を実現しようとしていた。When implemented on a semiconductor integrated circuit, it is difficult to make the resistance values equal to % by using a resistor element whose length is % of a resistor element having a certain basic length. Therefore, as shown in FIG. 2, an attempt was made to realize an accurate resistance ratio by connecting in parallel elements having the same structure and arranged at the same spacing and in the same direction.
[発明が解決しようとする課題]
しかし第2図の様な配置方法をしても素子31.34の
様に別の端に配置された素子は、隣接しているトランジ
スタ37や、別電源系のウェル38等周辺回路の影響に
より素子31.34と素子32.33の電気的特性に差
が生じ正確な抵抗比を得にくいという問題点を有してい
た。[Problems to be Solved by the Invention] However, even if the arrangement method shown in FIG. Due to the influence of peripheral circuits such as the well 38, there is a difference in the electrical characteristics of the elements 31, 34 and 32, 33, resulting in a problem that it is difficult to obtain an accurate resistance ratio.
そこで本発明は上記問題点を簡単な付加操作で素子の電
気的特性を同じくして、より精度の高いアナログ回路を
実現することを目的とする。Therefore, an object of the present invention is to solve the above-mentioned problems by making the electrical characteristics of elements the same through simple additional operations and realizing a more accurate analog circuit.
[課題を解決するための手段]
上記問題点を解決する為、本発明の半導体集積装置は、
半導体基板上に同一もしくは類似構造で同一サイズの複
数の抵抗素子を一定の規則で配置した抵抗素子群に対し
、配列の少なくとも片端に前記抵抗素子群の配列規則と
同一の規則で同一もしくは類似構造で同一サイズのダミ
ー抵抗素子を設けたことを特徴とする。[Means for Solving the Problems] In order to solve the above problems, the semiconductor integrated device of the present invention has the following features:
For a resistive element group in which a plurality of resistive elements having the same or similar structure and the same size are arranged in a certain order on a semiconductor substrate, at least one end of the array is provided with the same or similar structure with the same rule as the arrangement rule of the resistive element group. The feature is that dummy resistance elements of the same size are provided.
[作 用]
抵抗、容量素子等の受動素子の電気的特性を等しくする
目的で、同一規則の配列に配置しても、パターンが格子
状に並んでいるためウェハーを露光する時の光の回折現
象により配列の中と外側ではレジストの感光具合が異な
る、又製造工程中のエツチングの進み具合がやはり配列
の中と外側で異なるなどの原因により、配列の端に位置
する受動素子は電気的特性に異が生じる。そこで配列の
端に実際には回路上で使用しないダミー素子を設けてお
くことにより、上記問題点を回避できる。[Function] In order to equalize the electrical characteristics of passive elements such as resistors and capacitors, even if they are arranged in the same regular arrangement, the patterns are arranged in a grid pattern, which causes diffraction of light when exposing the wafer. Due to phenomena such as the photosensitivity of the resist being different between the inside and outside of the array, and the progress of etching during the manufacturing process also being different between the inside and outside of the array, the electrical characteristics of passive elements located at the ends of the array may vary. There will be a difference. Therefore, the above problem can be avoided by providing dummy elements that are not actually used on the circuit at the ends of the array.
[実 施 例] 本発明の実施例を第1図をもとに説明する。[Example] An embodiment of the present invention will be explained based on FIG.
素子21〜26は同じ構造同じサイズを持った拡散抵抗
素子で、全て同じ方向、同じ間隔(距離L)で配置され
ており、抵抗値はRである。素子21.22.23は3
本並列接続され、Z、(=R/3)として動作する。素
子24は1本で使用されZ2 (=R)として動作す
る。素子25.26は抵抗値Rであるが、他の素子と接
続はされずダミー抵抗として動作する。ただし他の抵抗
素子と同じ位置にコンタクトは設けておく。さらに基板
電位を安定させる為、ストッパー29を全ての抵抗素子
の周辺へ全ての抵抗素子から同じ距離になる様に配置し
ておく。The elements 21 to 26 are diffused resistance elements having the same structure and the same size, and are all arranged in the same direction and at the same interval (distance L), and have a resistance value R. Elements 21, 22, 23 are 3
This is connected in parallel and operates as Z, (=R/3). One element 24 is used and operates as Z2 (=R). Although the elements 25 and 26 have a resistance value R, they are not connected to other elements and operate as dummy resistors. However, the contacts are provided at the same position as other resistance elements. Furthermore, in order to stabilize the substrate potential, stoppers 29 are arranged around all the resistive elements so as to be at the same distance from all the resistive elements.
この様な配置方法により増幅回路を構成すると第3図に
おいて、入力電圧41 (V IN)と出力電圧42
(Vout )の関係は、
となる。この時素子21.22.23.24はダミー抵
抗25.26がある為、製造工程中のエツチングの進み
方及び拡散の深さ・広がり方が等しくなり、従って電気
的特性が均一となる為、Z2 :Z+=3:1
−・・ (11)という抵抗比の精度が向上する。よ
って、VOUT = 3 * V IN ・
・・ (12)となり増幅回路としての性能が向上する
。When an amplifier circuit is constructed using this arrangement method, the input voltage 41 (V IN) and the output voltage 42 are
The relationship between (Vout) is as follows. At this time, since the elements 21, 22, 23, 24 have dummy resistors 25, 26, the progress of etching during the manufacturing process and the depth and spread of diffusion are the same, and therefore the electrical characteristics are uniform. Z2 :Z+=3:1
-... (11) The accuracy of the resistance ratio is improved. Therefore, VOUT = 3 * V IN ・
...(12) The performance as an amplifier circuit is improved.
第4図はダミー素子群の別の配置例である。もしチップ
面積上杵されるならばダミー素子群48を使用する素子
群49の上下左右へ配置すればさらに抵抗比の精度は向
上する。FIG. 4 shows another arrangement example of the dummy element group. If the chip area is to be increased, the accuracy of the resistance ratio can be further improved by arranging the dummy element groups 48 above, below, and to the left and right of the element group 49 to be used.
又本実施例では素子25.26をダミー素子としたが、
素子21〜24を使用する回路とは別の回路系で使用し
ても、素子21〜24の特性の均一性は失われない。こ
の様に素子21と25の特性を厳密に合わせなくても良
い場合、ダミー素子25.26の分だけチップ面積がむ
だにならずに済む。Also, in this example, elements 25 and 26 were used as dummy elements, but
Even if the elements 21 to 24 are used in a circuit system different from the circuit in which they are used, the uniformity of the characteristics of the elements 21 to 24 is not lost. In this way, when the characteristics of the elements 21 and 25 do not have to be precisely matched, the chip area is not wasted by the dummy elements 25 and 26.
第5図は使用素子群とダミー素子群51の別の配置例で
ある。使用する素子52〜55と56〜59を二列に分
けて配置し、素子52.55.56.59の外側にダミ
ー素子60.61.62.63を配置する。FIG. 5 shows another arrangement example of the used element group and the dummy element group 51. The elements 52 to 55 and 56 to 59 to be used are arranged in two rows, and dummy elements 60.61.62.63 are arranged outside of the elements 52.55.56.59.
上記実施例では抵抗素材として拡散抵抗を説明したが、
ポリシリコン抵抗でも同様の効果がある。In the above embodiment, diffused resistance was explained as the resistance material.
A polysilicon resistor has a similar effect.
さらに本発明の構成方法は抵抗素子のみならず容量素子
、コイル、トランジスタ等へも適用可能である。Furthermore, the configuration method of the present invention is applicable not only to resistive elements but also to capacitive elements, coils, transistors, and the like.
本発明の実施例をもう一つ述べておく。第6図はラダー
抵抗器D/A変換回路図である。3ビツトのデジタルデ
ータ信号73.74.75により基準電圧70 (V
IN)を8段階に分は出力電圧71(VOIIT)とし
て取り出す。Another embodiment of the present invention will be described. FIG. 6 is a diagram of a ladder resistor D/A conversion circuit. The reference voltage 70 (V
IN) is extracted in eight stages as an output voltage 71 (VOIIT).
さらに詳しく動作を説明する。素子80〜87は本発明
の構成法によって配置された抵抗素子で、(第1図の配
置を拡張し、13本の素子の内両端の2本をダミー素子
とする)、素子80〜83・87は抵抗値Rとし、素子
84〜86は2本を直列接続して抵抗値2Rとする。そ
してトランジスタスイッチ76〜78・88〜90のオ
ン抵抗に対してRの値を100倍以上太き(設定し、ト
ランジスタスイッチのオン抵抗を無視できる様に定数設
定をしておく。するとデジタル信号73〜75の°°H
°°、” L ”にかかわらず、I++=Io +I+
o=2 Io =11 ・・ (13)■、□=L
+IIl:2I+ =I2・・(14)IIN=12+
I+□=2I2=IIN・・ (15)(但し素子81
〜86を流れる電流を各々Lo、III、III1、工
。、I−、I2.又信号70より流れ込む電流をIIN
とする)
つまり工。=iとすると
I + = 21 ・
・ ・ (17)I2 =4i
・ ・ ・ 〔18)となり信号70から信号7
2に流れる電流IsはI s=4 i *D7S+2
i *D74+ i D7a・・ (19)
となる。(例えば信号75が°°H°゛ならD75=1
、” L ”ならばD7.=φとする)よって出力電圧
はIsと抵抗素子80によって決まり、上式%式%)
ここで例えば素子86の抵抗値が他の素子の抵抗値より
大きくなると、デジタルデータD72、D74、D t
5に対する出力電圧特性の直線性が劣る。そこで本発明
の配置方法を適用することにより、素子80〜86の抵
抗値が均一になり、D/A変換器としての性能が向上す
る。The operation will be explained in more detail. Elements 80 to 87 are resistance elements arranged according to the construction method of the present invention (the arrangement shown in FIG. 1 is expanded, and two of the 13 elements at both ends are used as dummy elements). 87 has a resistance value R, and two elements 84 to 86 are connected in series to have a resistance value 2R. Then, set the value of R to be at least 100 times thicker than the on-resistance of the transistor switches 76 to 78 and 88 to 90, and set a constant so that the on-resistance of the transistor switch can be ignored.Then, the digital signal 73 ~75°°H
°°, regardless of “L”, I++=Io +I+
o=2 Io =11... (13) ■, □=L
+IIl:2I+ =I2...(14)IIN=12+
I+□=2I2=IIN... (15) (However, element 81
The currents flowing through ~86 are Lo, III, III1, and F, respectively. , I-, I2. Also, the current flowing from signal 70 is IIN
) In other words, engineering. = i then I + = 21 ・
・ ・ (17) I2 = 4i
・ ・ ・ [18] From signal 70 to signal 7
The current Is flowing through 2 is I s=4 i *D7S+2
i *D74+ i D7a... (19) (For example, if the signal 75 is °°H°゛, D75=1
, “L” then D7. = φ) Therefore, the output voltage is determined by Is and the resistance element 80, and the output voltage is determined by the above formula (% formula %) Here, for example, if the resistance value of the element 86 becomes larger than the resistance value of the other elements, the digital data D72, D74, D t
The linearity of the output voltage characteristics with respect to 5 is poor. Therefore, by applying the arrangement method of the present invention, the resistance values of the elements 80 to 86 become uniform, and the performance as a D/A converter is improved.
[発明の効果]
本発明は、複数の抵抗、容量、トランジスタ等の回路素
子を使う場合において、簡単なダミー素子を設けるとい
う簡単な追加操作により、ダミー素子にはさまれた全て
の素子の電気的特性を均一にし、回路の性能を向上する
ことができる。[Effects of the Invention] When using a plurality of circuit elements such as resistors, capacitors, transistors, etc., the present invention can reduce the electricity of all the elements sandwiched between the dummy elements by a simple additional operation of providing a simple dummy element. It is possible to make the physical characteristics uniform and improve the performance of the circuit.
又本発明はプロセス技術が変わっても適用できるもので
高精度アナログ回路を実現する上で極めて応用範囲が広
い。Furthermore, the present invention can be applied even if process technology changes, and has an extremely wide range of applications in realizing high-precision analog circuits.
第1図は本発明による回路素子の配置図、第2図は従来
の回路素子配置図、第3図は増幅回路図、第4図は、本
発明によるダミー素子配置図、第5図は本発明による他
のダミー素子配置図、第6図はラダー抵抗型D/A変換
回路図である。
以上FIG. 1 is a layout diagram of circuit elements according to the present invention, FIG. 2 is a conventional circuit element layout diagram, FIG. 3 is an amplifier circuit diagram, FIG. 4 is a dummy element layout diagram according to the present invention, and FIG. Another dummy element arrangement diagram according to the invention, FIG. 6, is a ladder resistance type D/A conversion circuit diagram. that's all
Claims (1)
の複数の抵抗素子を一定の規則で配置した抵抗素子群に
対し、配列の少なくとも片端に前記抵抗素子群の配列規
則と同一の規則で、同一もしくは類似構造で同一サイズ
のダミー抵抗素子を設けたことを特徴とする半導体集積
装置。For a resistive element group in which a plurality of resistive elements of the same or similar structure and the same size are arranged in a fixed order on a semiconductor substrate, at least one end of the array is arranged with the same or similar arrangement rule as the resistive element group. A semiconductor integrated device characterized in that a dummy resistance element having a similar structure and the same size is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63221925A JP3028420B2 (en) | 1988-09-05 | 1988-09-05 | Semiconductor integrated device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63221925A JP3028420B2 (en) | 1988-09-05 | 1988-09-05 | Semiconductor integrated device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0269972A true JPH0269972A (en) | 1990-03-08 |
JP3028420B2 JP3028420B2 (en) | 2000-04-04 |
Family
ID=16774307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63221925A Expired - Lifetime JP3028420B2 (en) | 1988-09-05 | 1988-09-05 | Semiconductor integrated device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3028420B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008111208A1 (en) * | 2007-03-15 | 2008-09-18 | Fujitsu Microelectronics Limited | Semiconductor integrated circuit |
JP2009206122A (en) * | 2008-02-26 | 2009-09-10 | Ricoh Co Ltd | Semiconductor device |
US8044450B2 (en) * | 2005-04-05 | 2011-10-25 | Kabushiki Kaisha Toshiba | Semiconductor device with a non-volatile memory and resistor |
US8225240B2 (en) | 2008-04-10 | 2012-07-17 | Renesas Electronics Corporation | Semiconductor device |
US8604589B2 (en) * | 2005-07-29 | 2013-12-10 | Seiko Instruments Inc. | Semiconductor device of polycrystalline silicon resistors |
JP2014099639A (en) * | 2014-01-15 | 2014-05-29 | Renesas Electronics Corp | Semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57128949A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Electric resistance device |
JPS57202774A (en) * | 1982-03-29 | 1982-12-11 | Nec Corp | Semiconductor device |
JPS5821365A (en) * | 1982-03-29 | 1983-02-08 | Nec Corp | Semiconductor integrated circuit device |
JPS6221260A (en) * | 1985-07-19 | 1987-01-29 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1988
- 1988-09-05 JP JP63221925A patent/JP3028420B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57128949A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Electric resistance device |
JPS57202774A (en) * | 1982-03-29 | 1982-12-11 | Nec Corp | Semiconductor device |
JPS5821365A (en) * | 1982-03-29 | 1983-02-08 | Nec Corp | Semiconductor integrated circuit device |
JPS6221260A (en) * | 1985-07-19 | 1987-01-29 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8044450B2 (en) * | 2005-04-05 | 2011-10-25 | Kabushiki Kaisha Toshiba | Semiconductor device with a non-volatile memory and resistor |
US8604589B2 (en) * | 2005-07-29 | 2013-12-10 | Seiko Instruments Inc. | Semiconductor device of polycrystalline silicon resistors |
WO2008111208A1 (en) * | 2007-03-15 | 2008-09-18 | Fujitsu Microelectronics Limited | Semiconductor integrated circuit |
JP5093224B2 (en) * | 2007-03-15 | 2012-12-12 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
US8637906B2 (en) | 2007-03-15 | 2014-01-28 | Fujitsu Semiconductor Limited | Semiconductor integrated circuit having polysilicon members |
JP2009206122A (en) * | 2008-02-26 | 2009-09-10 | Ricoh Co Ltd | Semiconductor device |
US8225240B2 (en) | 2008-04-10 | 2012-07-17 | Renesas Electronics Corporation | Semiconductor device |
JP2014099639A (en) * | 2014-01-15 | 2014-05-29 | Renesas Electronics Corp | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP3028420B2 (en) | 2000-04-04 |
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