JPS6235661A - Trimming method - Google Patents

Trimming method

Info

Publication number
JPS6235661A
JPS6235661A JP60175205A JP17520585A JPS6235661A JP S6235661 A JPS6235661 A JP S6235661A JP 60175205 A JP60175205 A JP 60175205A JP 17520585 A JP17520585 A JP 17520585A JP S6235661 A JPS6235661 A JP S6235661A
Authority
JP
Japan
Prior art keywords
trimming
terminal
potential
circuit
trimmed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60175205A
Other languages
Japanese (ja)
Other versions
JPH0571140B2 (en
Inventor
Shigeru Kawada
川田 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60175205A priority Critical patent/JPS6235661A/en
Publication of JPS6235661A publication Critical patent/JPS6235661A/en
Publication of JPH0571140B2 publication Critical patent/JPH0571140B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To carry out trimming after predicting the positions and bits to be trimmed by a method wherein the potential of a test terminal, provided in addition to a trimming terminal, is controlled in several steps before trimming operation. CONSTITUTION:In a reference voltage generating circuit, the potential of a test terminal 19 is controlled before trimming operation and the output potentials of an output terminal 8 corresponding to the respectively controlled potentials of the output terminal 19 are measured and positions, bits and so forth which are to be trimmed are predicted in accordance with those measured values and then trimming is carried out. With this constitution, defects of trimming failures caused by errors of positions, bits and so forth which are to be trimmed induced by discrepancies from originally designed values owing to misjudgement, element variation and production deviation at the time of integrated circuits or the like are significantly reduced and can be suppressed to the minimum level.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トリミング方式に係り、特に所望の増幅利得
を抵抗および、または容量等の値を調整することにより
得る類のトリミング回路において、トリミングすべき箇
所ならびにビット等の予測方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trimming method, particularly in a trimming circuit that obtains a desired amplification gain by adjusting the values of resistors and/or capacitors. This relates to a method for predicting locations to be used and bits.

〔従来の技術〕[Conventional technology]

集積回路等に2いて、トリミングを施すことにより、本
来所望の値に正確に調整しなければならない場合が多々
存在する。例えば、ディジタル・アナログ変換器(以下
DACと記す)2工び、アナログ・ディジタル変換器(
以下人DCと記す)等を構成する際に、DACの基準電
圧は、そのDACお工び入DCの変換精度を高く保つた
めに高精度でなおかつ、所望の絶対値を正確に得る必要
がある。係る場合に3いて、従来はトリミングと言う技
術を用いて基準電圧発生回路の帰還量等を調整し所望の
値を得てきた。
There are many cases where it is necessary to precisely adjust the value to the originally desired value by trimming the integrated circuit or the like. For example, two digital-to-analog converters (hereinafter referred to as DAC), two analog-to-digital converters (hereinafter referred to as DAC),
When configuring a DAC (hereinafter referred to as human DC), the reference voltage of the DAC needs to be highly accurate and accurately obtain the desired absolute value in order to maintain high conversion accuracy of the DAC manufactured by the DC. . In such cases, conventionally, a technique called trimming has been used to adjust the amount of feedback of the reference voltage generating circuit to obtain a desired value.

集積回路技術により形成された基準電圧発生回路の従来
例の説明図を第2図に示す。第2図は安定化電圧発生回
路1の出力端子(2001)を、出力端子(2002)
  エリ反転入力端子II(2003)へ帰還回路が形
成されるように構成された演算された演算増幅器2の非
反転入力端子INに接続し、トリミングにより抵抗30
1ないし308エリ成る抵抗例に2いて帰還抵抗となる
抵抗Rsと入力抵抗となる抵抗R3の抵抗比を調整し、
その演算増幅器2番こかかる増幅度を変化させ所望の基
準電圧を得るところの基準電圧発生回路である。尚ここ
では説明を簡単にするべく抵抗比の選択条件は8通りと
している。また第2図に2いて7は緩衝接続された演算
増幅器、8は基準電圧発生回路の出力端子を表わし、M
OSトランジスタ401〜424は反転回路501〜5
03と共に選択回路を構成し、これら選択回路は、正電
圧端子9と負電圧端子16に一端を接続された抵抗15
との間に並列に接続された3組の高抵抗1001〜10
03゜抵抗1101〜1103.  低抵抗値を持つ切
断部1201〜1203の直列接続回路、忘よびトリミ
ング用端子1301〜1303. 14エリ成る被トリ
ミング回路にて制御される。係る基準電圧発生回路に2
いてMOSトランジスタ401〜424 がN型の導通
特性を持つものと仮定して説明する。トリミングを施す
以前のこの基準電圧発生回路の状態は、被トリミング回
路に2ける切断部1201〜1203 が切断されてい
ないため、高抵抗1001と抵抗1101の接続点20
11、高抵抗1002と抵抗1102の接続点2012
.2よび高抵抗1003と抵抗1103の接続点201
3は全て低電位となって2つ、反転回路501,502
−J6Lび503の出力2014,2015.2工び2
01Gはそれぞれ高電位となっている。このためMOS
トランジスタ401〜424のうち、401.402.
2よび403のみが導通状態となり、演算増幅器2の出
力端子2002はMOS)ランジスタ401,402.
2工び403を通して演算増11福器2の反転入力端子
I!、2003に接続され、な2かつ、抵抗301゜3
02、・・・、308を通して接地電位6に接続され、
演算増幅器2の増幅度はlとなり、基準電圧発生回路の
出力端子8には、安定化電圧発生回路1の出力電圧その
tのが出力される。
FIG. 2 shows an explanatory diagram of a conventional example of a reference voltage generating circuit formed using integrated circuit technology. Figure 2 shows the output terminal (2001) of the stabilizing voltage generation circuit 1 and the output terminal (2002)
It is connected to the non-inverting input terminal IN of the operational amplifier 2 configured to form a feedback circuit to the inverting input terminal II (2003), and the resistor 30 is connected by trimming.
In the example of a resistor consisting of 1 to 308 areas, adjust the resistance ratio of the resistor Rs serving as the feedback resistor and the resistor R3 serving as the input resistor,
This is a reference voltage generation circuit that changes the amplification degree of the second operational amplifier to obtain a desired reference voltage. Here, in order to simplify the explanation, there are eight resistance ratio selection conditions. Further, in FIG. 2, 2 and 7 represent a buffer-connected operational amplifier, 8 represents an output terminal of a reference voltage generation circuit, and M
OS transistors 401-424 are inverting circuits 501-5
03 constitutes a selection circuit, and these selection circuits include a resistor 15 whose one end is connected to the positive voltage terminal 9 and the negative voltage terminal 16.
Three sets of high resistances 1001 to 10 connected in parallel between
03°Resistance 1101-1103. A series connection circuit of cutting parts 1201 to 1203 having a low resistance value, forgetting and trimming terminals 1301 to 1303. It is controlled by a trimmed circuit consisting of 14 areas. 2 in the reference voltage generation circuit.
The explanation will be made assuming that the MOS transistors 401 to 424 have N-type conduction characteristics. The state of this reference voltage generation circuit before trimming is that the connection point 20 between the high resistance 1001 and the resistance 1101 is the same as that at the connection point 20 between the high resistance 1001 and the resistance 1101, since the cutting portions 1201 to 1203 in the circuit to be trimmed are not cut.
11. Connection point 2012 between high resistance 1002 and resistance 1102
.. 2 and the connection point 201 between the high resistance 1003 and the resistance 1103
3 are all at low potential, and there are two inverting circuits 501 and 502.
-J6L Bi503 output 2014, 2015.2 work 2
01G each has a high potential. For this reason, MOS
Among the transistors 401 to 424, 401.402.
2 and 403 are in a conductive state, and the output terminal 2002 of the operational amplifier 2 is connected to the MOS transistors 401, 402 .
Inverting input terminal I of arithmetic increaser 11 lucky device 2 through 2-way 403! , 2003, and a resistor of 301°3.
02, . . . , connected to the ground potential 6 through 308,
The amplification degree of the operational amplifier 2 is 1, and the output voltage t of the stabilized voltage generation circuit 1 is outputted to the output terminal 8 of the reference voltage generation circuit.

このような回路に2いて、従来は、トリミングを行なう
以前に出力端子8の電圧を測定し、その値番こエリ切断
部1206,1202.2工び1203のいづれかある
いはそれら切断部の組み合わせを切断するかを一義的に
決定しトリミングを行なってきた。すなわち、トリミン
グを行なう以前に出力端子8における基準電圧発生回路
の出力電圧を測定し、その測定値より演算増幅器2の帰
還回路の抵抗比す表わち増幅度を決定し切断部1201
,1202、および1203のうちトリミングすべき箇
所ならびにビット等を決定してトリミング用端子14を
低電圧4子16と同電位に接αし、トリミングを施した
い切断部、たとえば1201の場合はトリミング端子1
301を正電圧端子8と同電位にすることにより切断部
1201を切断し、トリミングを行ない所望の基準電圧
を得ていた。
Conventionally, in such a circuit, the voltage at the output terminal 8 is measured before trimming, and one of the cutting portions 1206, 1202, 2 cutting portions 1203, or a combination of these cutting portions is cut. We have decided to make a clear decision as to whether or not to use the trimming method. That is, before trimming, the output voltage of the reference voltage generation circuit at the output terminal 8 is measured, and from the measured value, the resistance ratio, that is, the amplification degree of the feedback circuit of the operational amplifier 2 is determined.
, 1202, and 1203 to be trimmed, and connect the trimming terminal 14 to the same potential as the low voltage quadruplets 16, and connect the trimming terminal 14 to the cut section to be trimmed, for example, in the case of 1201. 1
The cutting portion 1201 is cut by setting the terminal 301 to the same potential as the positive voltage terminal 8, and trimming is performed to obtain a desired reference voltage.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のトリミング方式によるトリミング作業に
おいて、トリミングすべき箇所ならびにビット等を決定
する場合、トリミング時における判断の誤J)Kより、
他の箇所ならびにビット等にトリミングを施してしまっ
たり、または、上述の従来例における基準電圧発生回路
のごとき、トリミングを施すことによって所望の値を得
る回路を含む集積回路等の製造時における素子変動、製
造偏差等による抵抗301〜308の抵抗値等、回路素
子定数のバラツキによる増幅度等の設計値よりのズレに
より、トリミングを行なった後の基準電圧値等トリミン
グによシ調整される値が本来所望の値を得られずに不良
品としてしまう確率が高いと言う欠点があった。
In the trimming work using the conventional trimming method described above, when determining the parts and bits to be trimmed, errors in judgment during trimming J) K.
Trimming may be applied to other parts or bits, or element fluctuations may occur during the manufacturing of integrated circuits, etc. that include circuits that obtain desired values by performing trimming, such as the reference voltage generation circuit in the conventional example mentioned above. , the resistance value of the resistors 301 to 308 due to manufacturing deviation, etc., and the value adjusted by trimming, such as the reference voltage value after trimming, may vary from the design value such as the amplification degree due to variations in circuit element constants. Originally, there was a drawback that there was a high probability that the desired value could not be obtained and the product would be defective.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、トリミングを施すべき回路のトリミング用端
子K、トリミングを施す以前K ) IJ ミンク用端
子とは別に設けられたテスト用端子の電位を何段階か制
御し、それぞれの電位に対するトリミングを施すべき回
路の出力を測定し、それらの測定値によシトリミングを
施すべき箇所ならびにビット等を予測してトリミングす
ると言う手段を有している。
The present invention controls the potentials of the trimming terminal K of the circuit to be trimmed and the test terminal provided separately from the IJ mink terminal in several stages, and performs trimming for each potential. It has a means for measuring the output of the power circuit and predicting and trimming the parts and bits to be trimmed based on the measured values.

〔実施例〕〔Example〕

以下に集積回路技術によシ形成された基準発生回路を例
にとり、図面を参照して本発明の詳細な説明する。
The present invention will be described in detail below with reference to the drawings, taking as an example a reference generation circuit formed by integrated circuit technology.

第1図に本発明の一実施例の説明図を示す。尚従来例と
して示した第2図と同一な箇所には同一の番号が付しで
ある。つまり、MOSトランジスタ401〜424およ
び反転回路501〜503より成る選択回路と正電端子
9、高抵抗1001〜1003、抵抗1101〜110
3.切断部1201〜1203、トリミング用端子13
01〜1303.14.抵抗15、および負電圧端子1
6より成る被トリミング回路との接続部において、高抵
抗1001と抵抗1101の接続点2011がMOSト
ランジスタ404,410゜416.422の各ゲート
端子および反転回路501の入力端子に接続され、高抵
抗1002と抵抗1102の接続点2012が2人力論
理和回路1701の1つの入力端子に接続され、この2
人力論理和回路の出力端子2019がMOSトランジス
タ408,411゜420.423の各ゲート端子およ
び反転回路502の入力端子に接続され、高抵抗100
3と抵抗1103(7)接続点2013が2人力論理和
回路17o2の1つの入力端子に接続され、この2人力
論理和回路1702の出力端子2020がMOSトラン
ジスタ415 、418’、 421.424の各ゲー
ト端子および反転回路503の入力端子に接続され、反
転回路501の出力端子2014がMOB)ランジスタ
401.407,413,419の各ゲート端子に接続
され、反転回路502の出力端子2o15がMOSトラ
ンジスタ402,405,414,417の各ゲート端
子に接続され、反転回路503の出力端子2o16がM
OB)ランジスタ403,406,409,412の各
ゲート端子に接続されテスト用端子19が選択器18の
入力端子に接続され、選択器18の第1の出力端子20
17が2人力論理和回路1701の他方の入力端子に接
続され、選択器18の第2の出力端子2018が2人力
論理和回路1702の他方の入力端子に接続されてなる
基準電圧発生回路である。ここで選択器2は第1表に示
すごとき動作を行ない、なおかつ抵抗301N307は
単位抵抗値R1,また、抵抗308は抵抗値R2と仮定
する。
FIG. 1 shows an explanatory diagram of an embodiment of the present invention. Note that the same parts as in FIG. 2 shown as a conventional example are given the same numbers. That is, a selection circuit consisting of MOS transistors 401 to 424 and inverting circuits 501 to 503, a positive terminal 9, high resistances 1001 to 1003, and resistors 1101 to 110.
3. Cutting parts 1201 to 1203, trimming terminal 13
01-1303.14. Resistor 15 and negative voltage terminal 1
6, a connection point 2011 between the high resistor 1001 and the resistor 1101 is connected to each gate terminal of the MOS transistors 404, 410, 416, and 422 and the input terminal of the inverting circuit 501, and the high resistor 1002 The connection point 2012 between the
The output terminal 2019 of the human-powered OR circuit is connected to each gate terminal of the MOS transistors 408, 411, 420, and 423 and the input terminal of the inverting circuit 502.
3 and the resistor 1103 (7) connection point 2013 is connected to one input terminal of the two-man power OR circuit 17o2, and the output terminal 2020 of this two-man power OR circuit 1702 connects each of the MOS transistors 415, 418', and 421.424. The output terminal 2014 of the inverting circuit 501 is connected to each gate terminal of MOB transistors 401, 407, 413, and 419, and the output terminal 2o15 of the inverting circuit 502 is connected to the MOS transistor 402. , 405, 414, and 417, and the output terminal 2o16 of the inverting circuit 503 is connected to the gate terminals of M
OB) The test terminal 19 connected to each gate terminal of the transistors 403, 406, 409, and 412 is connected to the input terminal of the selector 18, and the first output terminal 20 of the selector 18
17 is connected to the other input terminal of the two-manpower OR circuit 1701, and the second output terminal 2018 of the selector 18 is connected to the other input terminal of the two-manpower OR circuit 1702. . Here, it is assumed that the selector 2 operates as shown in Table 1, and the resistor 301N307 has a unit resistance value R1, and the resistor 308 has a resistance value R2.

以下余白、5.・↑[、パか、 第1表 係る基準電圧発生回路において、トリミングをす以前に
、テスト用端子19の電位を制御し、それぞれの電位に
対する基準電圧発生回路の出力端子8の出力電位を測定
し、それらの測定値によリドリミングを施すべき箇所な
らびにビット等を予測してトリミングを施す、つまり、
テスト用端子19を正電圧電源に接続し九とすると、第
1表に示すごとく選択器18の第1の出力端子2017
、第2の出力端子2018は共に低論理電位となシ、2
人力論理和回路1701の出力端子2o19は入力端子
2012がトリミング前なので低電位であるた低電位と
なる。又2人力論理和回路1702の出方端子2020
も同様に入力端子2013がトリミング前なので低電位
であるため低電位となる。更に高抵抗1001と抵抗1
101との接続点2011も低電位であるために、反転
回路501,502.および503の全ての出力それぞ
れ2014,2015.および2016が高電位どなり
、MOSトランジスタ401.402,403,405
,406,407,409゜412.413,414,
417、および419が導通状態となり、他のMOB)
ランジスタが非導通状態となり、演算増幅器2の出力端
子2002はMOSトランジスタ401,402を通し
て反転入力端子IE2003に接続される。この時の出
力端子8の出力電位をVngrlとする。また安定化電
圧発生回路1の出力端子2001の電位をΔVT、およ
び演算増幅器7の出力オフセット電位をVxoとすると
、ΔvT=vREF1−vlOψ日・・(1)となる。
Margin below, 5.・↑[, Paka, Table 1 In the reference voltage generation circuit according to the above, before trimming, the potential of the test terminal 19 is controlled, and the output potential of the output terminal 8 of the reference voltage generation circuit is measured for each potential. Then, based on these measured values, the parts and bits that should be retrimmed are predicted and trimmed.
If the test terminal 19 is connected to a positive voltage power supply and set to 9, the first output terminal 2017 of the selector 18 as shown in Table 1.
, the second output terminal 2018 are both at low logic potential, 2
The output terminal 2o19 of the manual OR circuit 1701 has a low potential since the input terminal 2012 is at a low potential before trimming. Also, the output terminal 2020 of the two-manpower OR circuit 1702
Similarly, since the input terminal 2013 is at a low potential before trimming, it becomes a low potential. Even higher resistance 1001 and resistance 1
Since the connection point 2011 with the inverting circuits 501, 502 . and all outputs of 503 2014, 2015, respectively. and 2016 are high potential, MOS transistors 401, 402, 403, 405
,406,407,409゜412.413,414,
417 and 419 become conductive, and other MOB)
The transistor becomes non-conductive, and the output terminal 2002 of the operational amplifier 2 is connected to the inverting input terminal IE2003 through the MOS transistors 401 and 402. The output potential of the output terminal 8 at this time is set to Vngrl. Further, if the potential of the output terminal 2001 of the stabilizing voltage generation circuit 1 is ΔVT, and the output offset potential of the operational amplifier 7 is Vxo, then ΔvT=vREF1−vlOψday (1).

次にテスト用端子19を接地電位に接続すると、第1表
に示すごとく、選択器18の第1の出力端子2017が
高論理電位、第2の出方端子2018が低論理電位とな
り、節点2011および節点2020は低電位、そして
節点2019が高電位となるこのためMOS)ランジス
タ401〜424のうち401,403,406,40
7,408,409゜411.412,413,419
,420、および423が導通状態となり他のMOS)
ランジスタは非導通状態となシ、抵抗302と抵抗30
3との接続点2005がM08トランジスタ407,4
08.409を通して演算増幅器2つの反転入力端子2
003に接続される。この時の出力端子8の出力電位を
Va針2 とすると となる。次にテスト用端子19を負電圧電源に接続する
と、第1表に示すごとく、選択器18の第1の出力端子
2017が低論理電位、第2の出力端子2018が高論
理電位となシ1節点2011および節点2019は低電
位、そして節点2020が高電位となる。このため、M
OSトランジスタ401〜424のうち401,402
,405.407,413゜414.415,417,
418,419,421、および424が導通状態とな
り、他のMOSトランジスタは非導通状態となり、抵抗
304と抵抗305との接続点2007がMOS)ラン
ジスタ413゜414.415  を通して演算増幅器
20反転入力端子112003に接続される。この時の
出力端子8の出力電位をVnl+I!3とすると となる。また抵抗301から数えて(、(11)番目と
n番目の抵抗の接続点がMOSトランジスタ3個を介し
て演算増幅器2の反転入力端子lI2003に接続され
是場合の出力端子8の出力電位をVR訂とすると と表わされる。ここで所望の基単電圧発生回路の出力電
圧VRKFを得ることのできる帰還点は(4)式%式%
(5) また、(1) 、 (2) 、 (3)式よりVlo 
= VREF l−ΔV’r     ・・・・・(6
)となり、トリミング前に行なった3図の測定によル測
定値VRIFI、VRlF 2、オ!ヒVngr 3 
j l)トリミングを施すべき回路ごとのトリミングす
べき箇所ならびにビット等が計算により正確に求められ
る。
Next, when the test terminal 19 is connected to the ground potential, as shown in Table 1, the first output terminal 2017 of the selector 18 becomes a high logic potential, the second output terminal 2018 becomes a low logic potential, and the node 2011 and the node 2020 is at a low potential, and the node 2019 is at a high potential.
7,408,409゜411.412,413,419
, 420, and 423 become conductive, and other MOS)
The transistors are in a non-conducting state, and the resistors 302 and 30
The connection point 2005 with 3 is the M08 transistor 407,4
08.409 through operational amplifier two inverting input terminals 2
Connected to 003. Let the output potential of the output terminal 8 at this time be Va needle 2. Next, when the test terminal 19 is connected to a negative voltage power supply, as shown in Table 1, the first output terminal 2017 of the selector 18 becomes a low logic potential and the second output terminal 2018 becomes a high logic potential. Node 2011 and node 2019 have a low potential, and node 2020 has a high potential. For this reason, M
401,402 of OS transistors 401 to 424
,405.407,413゜414.415,417,
418, 419, 421, and 424 are in a conductive state, the other MOS transistors are in a non-conductive state, and the connection point 2007 between the resistor 304 and the resistor 305 is connected to the inverting input terminal 112003 of the operational amplifier 20 through the MOS transistors 413, 414, and 415. connected to. The output potential of the output terminal 8 at this time is Vnl+I! If it is 3, then it becomes. In addition, the connection point between the (11)th and nth resistors counting from the resistor 301 is connected to the inverting input terminal lI2003 of the operational amplifier 2 via three MOS transistors, and the output potential of the output terminal 8 is set to VR. Here, the feedback point at which the desired output voltage VRKF of the base single voltage generation circuit can be obtained is expressed by equation (4).
(5) Also, from equations (1), (2), and (3), Vlo
= VREF l−ΔV'r (6
), and the measured values VRIFI, VRIF 2, O! are obtained from the measurements shown in Figure 3 performed before trimming. Hi Vngr 3
j l) The location to be trimmed, bits, etc. for each circuit to be trimmed can be accurately determined by calculation.

この様なAl1によりトリミングを行なう以前に、切断
部を一切切断せずに正確にトリミングを捲すべき箇所な
らびにビット等をトリミングを怖し所望の出力を得る回
路ごとに予測でき、そめ後にトリミングを施すことがで
きる。
Before performing trimming using Al1, it is possible to accurately predict the parts and bits to be trimmed without cutting any parts, for each circuit to avoid trimming and obtain the desired output, and then perform trimming after trimming. can be administered.

また(1)〜(8)式よりわかる様に、トリミングを施
し所望の出力を得る回路ごとの素子変動、製造偏差等に
よる安定化電圧発生回路の出力電圧ΔTr、演算増幅器
7の出力オフセット電圧Vro  および抵抗301〜
307の抵抗値R1と抵抗308の抵抗値R2との比R
t/R1等のバラツキがあった場合でも正確にトリミン
グを施すべき箇所ならびにビット等を予測できる。
In addition, as can be seen from equations (1) to (8), the output voltage ΔTr of the stabilizing voltage generation circuit due to element variations in each circuit to obtain the desired output by trimming, manufacturing deviation, etc., and the output offset voltage Vro of the operational amplifier 7 and resistance 301~
Ratio R between resistance value R1 of resistor 307 and resistance value R2 of resistor 308
Even if there are variations in t/R1, etc., it is possible to accurately predict the location and bits to be trimmed.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように、本発明を用いてトリミングを権
す以前にトリミングを施すべき箇所ならびにビット等を
正確に予測でき、その後トリミングを施すことができる
ため、判断の誤りや、H66回路等の製造時における素
子変動、製造偏差等による本来設計した値よりのズ1ノ
等によるトリミングを施すべき箇所ならびにビット等の
誤シによるトリミング失敗の不良の発生を著しく減少さ
せ、最小限におさえることができる。なおかつトリミン
グに費される時間をも節約でき、集積回路等の応用に非
常に有効である。
As described above, by using the present invention, it is possible to accurately predict the parts and bits to be trimmed before trimming, and trimming can be performed afterward. It is possible to significantly reduce and minimize the occurrence of defects such as trimming failures due to errors in parts and bits that should be trimmed due to deviations from the originally designed value due to element variations and manufacturing deviations during manufacturing. can. Furthermore, the time spent on trimming can also be saved, making it very effective for applications such as integrated circuits.

また、上述の集積回路とは、半導体集積回路のみならず
混成集積回路にも応用できる事はあきらかである。更に
、トリミング用端子とは別に設けたテスト用端子は1つ
とは限らず複数個用意して更に多くの種類の測定が可能
になる様にすることも可能である事はあきらかである。
Furthermore, it is obvious that the above-mentioned integrated circuit can be applied not only to semiconductor integrated circuits but also to hybrid integrated circuits. Furthermore, it is obvious that the number of test terminals provided separately from the trimming terminals is not limited to one, but that a plurality of test terminals may be provided to enable even more types of measurements.

また、本実施例では基準電圧発生回路のトリミングを例
にとって説明を行なったが、他のトリミングを施し所望
の出力を得る類の回路のトリミングに本方式を用いる事
ができるのはあきらかである。
Further, although this embodiment has been explained by taking trimming of a reference voltage generation circuit as an example, it is obvious that the present method can be used for trimming other types of circuits that obtain a desired output by performing other trimming.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の説明図、また第2図は従来
例の説明図である。 なお図において、1・・・・・・安定化電圧発生回路、
2.7・・・・・・演算増幅器、301〜308.10
01S1003.1101〜1103.15  ・−・
・−抵抗、401〜424・・・・・・MOSトランジ
スタ、501〜503・・・・・・反転回路、6・・・
・・・接地電位、8・・・・・・出力端子、9・・・・
・・正電圧端子、1201〜1203・・・・・・切断
部、1301〜1303.14・・・・・・トリミング
用端子、16・・・・・・負電圧端子、1701.17
02・・・・・・2人力論理和回路、18・・・・・・
選択器、19・・・・・・テスト用端子、2001〜2
020・・・・・・節点である。
FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional example. In the figure, 1... stabilizing voltage generation circuit,
2.7...Operation amplifier, 301-308.10
01S1003.1101-1103.15 ・-・
-Resistor, 401-424...MOS transistor, 501-503...Inverting circuit, 6...
...Ground potential, 8...Output terminal, 9...
... Positive voltage terminal, 1201-1203... Cutting section, 1301-1303.14... Trimming terminal, 16... Negative voltage terminal, 1701.17
02...2 human-powered OR circuit, 18...
Selector, 19...Test terminal, 2001-2
020... It is a node.

Claims (1)

【特許請求の範囲】[Claims]  トリミングを施すべき回路のトリミング用端子に、ト
リミングを施す以前にトリミング用端子とは別に設けら
れたテスト用端子の電位を制御し、該テスト用端子のそ
れぞれの電位に対する該トリミングを施すべき回路の出
力を測定し、該測定値によりトリミングを施すべき箇所
を選択しトリミングを行なうことを特徴とするトリミン
グ方式。
Before performing trimming on the trimming terminal of the circuit to be trimmed, the potential of a test terminal provided separately from the trimming terminal is controlled, and the voltage of the circuit to be trimmed is adjusted for each potential of the test terminal. A trimming method characterized by measuring the output, selecting the area to be trimmed based on the measured value, and performing the trimming.
JP60175205A 1985-08-09 1985-08-09 Trimming method Granted JPS6235661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60175205A JPS6235661A (en) 1985-08-09 1985-08-09 Trimming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60175205A JPS6235661A (en) 1985-08-09 1985-08-09 Trimming method

Publications (2)

Publication Number Publication Date
JPS6235661A true JPS6235661A (en) 1987-02-16
JPH0571140B2 JPH0571140B2 (en) 1993-10-06

Family

ID=15992129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60175205A Granted JPS6235661A (en) 1985-08-09 1985-08-09 Trimming method

Country Status (1)

Country Link
JP (1) JPS6235661A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972144A (en) * 1989-11-28 1990-11-20 Motorola, Inc. Testable multiple channel decoder
US5175547A (en) * 1992-01-31 1992-12-29 Motorola, Inc. Method and apparatus for testing an analog to digital converter
US5185607A (en) * 1992-01-31 1993-02-09 Motorola, Inc. Method and apparatus for testing an analog to digital converter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50129960A (en) * 1974-03-20 1975-10-14
JPS55150207A (en) * 1979-05-11 1980-11-22 Hitachi Ltd Trimming device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50129960A (en) * 1974-03-20 1975-10-14
JPS55150207A (en) * 1979-05-11 1980-11-22 Hitachi Ltd Trimming device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972144A (en) * 1989-11-28 1990-11-20 Motorola, Inc. Testable multiple channel decoder
US5175547A (en) * 1992-01-31 1992-12-29 Motorola, Inc. Method and apparatus for testing an analog to digital converter
US5185607A (en) * 1992-01-31 1993-02-09 Motorola, Inc. Method and apparatus for testing an analog to digital converter

Also Published As

Publication number Publication date
JPH0571140B2 (en) 1993-10-06

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