JPH0265273A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease Al spikes in a contact hole so as to improve a semiconductor device in reliability by a method wherein a dummy contact hole not contributing the operation of a transistor is provided near to a contact hole contributing the operation of a transistor. CONSTITUTION:A dummy contact hole section 2 other than a contact hole section 1 conductive to the transistor operation is provided near to the contact hole section 1, and Si is made to diffuse into Al through the dummy contact hole section 2, whereby Al spikes are restrained from occurring in the active contact hole section 1. The dummy contact hole 2 is provided within such a distance from the contact hole section 1 that Si can diffuse within an annealing time. By these processes, the effect of restraining spikes from occurring can be realized and the failure such as an interlaminar current leakage or the like can be decreased.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor device formed on a semiconductor substrate or an insulating substrate, and more specifically, to an AQ in the semiconductor device.
Related to wiring technology.

[Conventional technology and its problems]

In semiconductor devices such as large-area devices using TPT with a polycrystalline silicon active layer on a semiconductor substrate or an insulating substrate, AQ or AQ-approximately 1% Si,
AQ gold alloys such as Afl--about 1% Cu are widely used.

Such AQ or AQ gold alloys must have low resistivity (i.e. 2.7 x 10-' Q ・an, less than 3.5 x 10-' Q -■ for alloys) and low resistance. In addition to satisfying the requirements for %N wiring,
It has very good adhesion to the SiO2 film.

However, since the AQ-8i alloy exhibits eutectic properties, AQ
After thin film deposition, S into AQ during the thermal history of various processes.
Dissolution of i occurs. FIG. 2 shows the phase diagram of AQ-8i. From this phase diagram, for example, the solubility of Si in AQ is 0.25 wt% at 400°C and 0.5w at 450°C.
t%, and 0.8 wt% at 500°C. Therefore, when AQ and Si are in contact with each other through the contact hole portion, Si becomes a solid solution in AQ according to its solubility corresponding to its temperature. However, it is known that solid solution exceeding the solubility limit actually occurs. Furthermore, the amount of Si dissolved in solid solution does not simply depend on the amount dissolved corresponding to the annealing temperature, but also depends on the volume of AQ saturated with Si. As a result of this solid solution of Si into AQ, it becomes as if AQ is sucking up Si and the Afl wiring protrudes in the vertical and horizontal directions (see Figure 3).
. This phenomenon is called an AQ spike, and is a problem in AQ and wiring technology.

That is, vertical spikes cause junction leakage and interlayer leakage, and horizontal spikes cause junction leakage.

As a countermeasure against this AQ spike, there is a method of simultaneously depositing AQ and Si, or using a sputtering method using an AQ-several percent Si alloy as a target, and adding Sj to AQ close to its solubility limit. However, AQ-several %Si
The contact resistance of the alloy increases, and it is difficult to form a good ohmic contact with n+ silicon. Furthermore, the dalein size becomes microscopic, which may lead to migration failure due to stress. especially,
A new problem has arisen regarding the reliability of large-area semiconductor devices (thin film transistors) formed on an insulating substrate using polycrystalline silicon as a semiconductor material, such as thin film transistors for driving sensors, liquid crystal panels, and thin film transistors for driving EL panels. Another measure to prevent AQ spikes is to insert a metal between the AQ and the Si substrate to act as a barrier. However, such means go against the original aim of simplifying the process steps, and instead complicate the process.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which takes measures against the above-mentioned AQ spike problem from a completely different perspective than conventional means.

[Means to solve the problem]

The present invention is a semiconductor device formed on a semiconductor substrate or an insulating substrate, characterized in that a contact that does not contribute to transistor operation is provided near a contact that operates as a transistor.

In the present invention, AQ spikes depend not only on the solubility of Si in AQ at the annealing temperature, but also on the volume of AQ saturated with Si.
The AQ/Si contact portion is intended to supply Si into the AQ from a contact interface separate from the actual drive portion, and to limit the diffusion of Si from the device drive contact portion.

Figure 4 shows the layout of a conventional CMO8 using polycrystalline silicon as a semiconductor material on a quartz substrate. A silicon gate and 5 indicate AQ wiring, respectively. In the device shown in FIG. 4, as described above, a spike of An progresses in the contact hole portion 1, and Si diffuses into the entire AQ wiring 5 in an amount corresponding to the annealing temperature. Therefore, in the present invention, the first
As shown in the figure, in addition to the contact hole part 1 involved in transistor operation, a dummy contact hole part 2 is provided near this contact hole 1, and Si is AQ-filled from this dummy contact hole part 2.

The AQ spike in the contact hole section 1 of the actual drive section is limited by diffusing the contact hole section 1 into the contact hole section 1 of the actual drive section. This dummy contact hole portion 2 is provided within a distance range within which Si diffuses within the annealing time with respect to the contact hole portion 1. The relational expression is L=v'Dt, where D is the diffusion coefficient and t is the annealing time. The diffusion coefficient of Si in the AQ deposited film is D = 4. OX 10-
”exp (-0,92/kt), therefore,
When annealing is performed at 500° C. for 30 minutes, L becomes approximately 607 zm. That is, the dummy contact hole section 2 is provided within the range of VDt from the center of the desired contact hole section 1 along the AQ wiring line.

Generally, the spike depth Q is expressed by the following equation.

Here, D = diffusion coefficient t: heat treatment time d: Afl film thickness W: contact width A: contact area S Si solubility in AQ at near annealing temperature ρ^hρsi: AΩ, Si density From above, spike depth Q is compared to the volume of AQ where Si is saturated. When the dummy contact hole portion 2 is formed as shown in FIG. 1, the theoretical value of the spike depth of the contact hole portion 1 is 1/4Q.

In the experiment, the temperature was 450℃ for 15 minutes, 30 minutes, 60 minutes, and 90 minutes.
Si wafer etch pits were observed using a SEM (scanning electron microscope) when the processing time was varied. In the CMOS layout of the conventional design shown in FIG. 4, the amount of etch pits in the contact hole portion 1 increased in proportion to the square root of time. On the other hand, in the new design of the CMO8 layout shown in Figure 1, the amount of etch pits is the same as the conventional design at 15 minutes, proportional to the fourth root from 30 minutes to 60 minutes, and completely different from 60 minutes to 90 minutes. I didn't.

Next, we calculated the ratio between the conventional design and the new design. The conditions and results are as follows.

Conditions Contact hole diameter 8μm x 8μm Heat treatment conditions 450℃, 60 minutes (in forming gas) SE
Erase pit calculated from the etch pit amount by M...After the AQ spike has progressed, wet etching is performed using a phosphoric acid or nitric acid based etchant.

Result Conventional/New design = 1.3X10-”a&/4.5X1
0-12 ad, that is, the depth of the spike was reduced to about ⅓.

From the above, according to the present invention, it is possible to reduce AQ spikes using pure AQ without using AQ gold alloy, which causes stress migration, as AQ wiring. In addition, when multilayer wiring is performed, Afl-several %
By applying a design as shown in FIG. 1 to wiring using a Si alloy film, it is possible to obtain the effect of limiting spikes and to reduce failures such as interlayer leakage.

[Action/effect of the invention]

In the present invention as described above, in a semiconductor device formed on a semiconductor substrate or an insulating substrate, a dummy contact hole portion that does not contribute to transistor operation is provided near the contact hole portion where the transistor operates. AM spikes in the contact hole area are reduced, and interlayer leakage caused by AQ spikes is reduced.
Junction leakage is reduced and reliability of semiconductor devices is improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a CMOS layout showing an embodiment of the present invention. FIG. 2 is a phase diagram of the AQ-8i system. FIG. 3 is a schematic explanatory diagram showing the AQ spike phenomenon. FIG. 4 is a plan view of a conventional CMOS layout. 1...Contact hole part 2...Dummy contact hole part 3...Polycrystalline silicon layer 4...Polysilicon gate 5...AQ wiring Fig. 2 wt%Si Fig. 4

Claims (1)

[Claims] 1. A semiconductor device formed on a semiconductor substrate or an insulating substrate, characterized in that a contact that does not contribute to transistor operation is provided near a contact that operates as a transistor.