JPH0256928A - Treatment of semiconductor wafer - Google Patents

Treatment of semiconductor wafer

Info

Publication number
JPH0256928A
JPH0256928A JP20768588A JP20768588A JPH0256928A JP H0256928 A JPH0256928 A JP H0256928A JP 20768588 A JP20768588 A JP 20768588A JP 20768588 A JP20768588 A JP 20768588A JP H0256928 A JPH0256928 A JP H0256928A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
processing
ion implantation
ultrasonic waves
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20768588A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20768588A priority Critical patent/JPH0256928A/en
Publication of JPH0256928A publication Critical patent/JPH0256928A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve the treatment performance and the performance of films by applying an ultrasonic wave to a semiconductor wafer in the ion implantation process of said semiconductor wafer. CONSTITUTION:An ultrasonic wave is applied to a semiconductor wafer in the ion implantation process of said semiconductor wafer, an ultrasonic wave is applied to the semiconductor wafer in the dry etching process of the semiconductor wafer, and an ultrasonic wave is applied to the semiconductor wafer, a gas source, or a deposition source in forming a CVD film and a deposition film on the semiconductor wafer. These improve the treatment performance, the performance of the films, and the controllability in the ion implantation and the dry etching processes of the semiconductor wafer and in forming the CVD film and the deposition film.

Description

【発明の詳細な説明】 [産業上の利用分野〕 本発明は、半導体ウェーハのイオン打込み処理、ドライ
エツチング処理及び、CVD膜や蒸着膜形成処理方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ion implantation process, a dry etching process, and a CVD film or vapor deposited film forming process for semiconductor wafers.

〔従来の技術1 従来、半導体ウェーハのイオン打込み処理、ドライエツ
チング処理及びCVD膜や蒸着膜形成時に超音波を基板
やソースに印加して処理する様な方法はなかった。
[Prior Art 1] Conventionally, there has been no method of applying ultrasonic waves to a substrate or source during ion implantation, dry etching, CVD film, or vapor deposition of semiconductor wafers.

[発明が解決しようとする課題) しかし、上記従来技術に対し、今回、半導体ウェーハの
イオン打込み処理やドライエツチング処理及びCVD膜
や蒸着膜の形成時に基板やソースに超音波を印加する事
により、これら処理性能や膜性能に新しい向上効果を見
つけたので、これらの処理性能や膜性能を向上する目的
で本発明を提供する。
[Problems to be Solved by the Invention] However, in contrast to the above-mentioned conventional technology, this time, by applying ultrasonic waves to the substrate and source during ion implantation processing, dry etching processing of semiconductor wafers, and formation of CVD films and vapor deposition films, Since we have found a new improvement effect on these processing performance and membrane performance, we provide the present invention for the purpose of improving these processing performance and membrane performance.

[課題を解決するための手段] 上記目的を達成するために、本発明は半導体ウェーハの
処理方法に間し、 (1)半導体ウェーハのイオン打込み処理時に半導体ウ
ェーハに超音波を印加する手段をとる事。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for processing a semiconductor wafer, which includes: (1) applying ultrasonic waves to the semiconductor wafer during ion implantation processing of the semiconductor wafer; case.

及び (2)半導体ウェーハのドライエツチング処理時に半導
体ウニ・−ハに超音波を印加する手段をとる事、及び (3)半導体ウェーハへのCV D n!形成時及び蒸
着膜形成時に半導体ウェーハ、あるいはガス′ソースあ
るいは蒸着ソースには超音波を印加する手段をとる事、 等である。
and (2) applying means for applying ultrasonic waves to the semiconductor wafer during dry etching processing of the semiconductor wafer, and (3) applying CVDn! to the semiconductor wafer. For example, applying ultrasonic waves to the semiconductor wafer, gas source, or deposition source during formation and deposition film formation.

[実 施 例1 以下、実施例により本発明を詳述する。[Implementation Example 1] Hereinafter, the present invention will be explained in detail with reference to Examples.

いま、Siウェーハにボロンあるいは填あるいは砒素等
のイオン打込み処理を行なうに際し、Slウェーハ表面
に水平に超音波を印加すると、ボロン・イオン打込みの
場合には最も激しく、チャンネリングが通常発生するの
に対し、超音波印加により、チャンネリング現象を防止
する事が出来る。チャンネリングを防止するには、今一
つの方法にSiウェーハを200℃〜300℃に加熱し
たり、予じめSiイオンを打込んでアモルファス化する
等の方法があるが、本発明の場合、これら従来技術に対
しイオン打込み部の活性化後の結晶欠陥の発生が少ない
等の効果もある。
Now, when implanting boron, filling or arsenic ions into Si wafers, if ultrasonic waves are applied horizontally to the surface of the Si wafer, this is most intense in the case of boron ion implantation, although channeling normally occurs. On the other hand, the channeling phenomenon can be prevented by applying ultrasonic waves. Other methods to prevent channeling include heating the Si wafer to 200°C to 300°C or implanting Si ions in advance to make it amorphous, but in the case of the present invention, these methods can be prevented. Compared to the conventional technology, there are also effects such as less generation of crystal defects after activation of the ion implantation part.

また、Siウェーハのドライエツチング時にSiウェー
ハに垂直に超音波を印加すると、エツチング速度が向上
し、Siウェーハの加熱処理が不要となったり、又、ト
レンチ・エッヂの溝形状が細くかつ深くでき、又、超音
波をSiウェーハに水平に印加したり、ftjll し
て印加さゼることにより、トレンチ・エッチの溝形状を
制御することもできる。
Furthermore, if ultrasonic waves are applied perpendicularly to the Si wafer during dry etching of the Si wafer, the etching speed will be improved, heat treatment of the Si wafer will not be necessary, and the groove shape of the trench edge can be made narrower and deeper. Furthermore, the groove shape of the trench etch can be controlled by applying ultrasonic waves horizontally or ftjll to the Si wafer.

更にSlウェーハのCVI)股やに着膜形成時に、Sl
ウェーハやソース超音波を印加する事により、つきまわ
りの良い、Llつ緻密な膜を形成する事ができる。
Furthermore, when forming a film on the crotch (CVI) of the Sl wafer,
By applying ultrasonic waves to the wafer or source, a dense film with good throwing power can be formed.

[発明の効果] 本発明により、半導体ウェーハのイオン打込み処理やド
ライエツチング処理あるいは、CVD膜や蒸着形成時の
処理性能や膜性能を向上させたりあるいは制御性を向上
さセることができる効果がある。
[Effects of the Invention] The present invention has the effect of improving processing performance and film performance during ion implantation processing and dry etching processing of semiconductor wafers, CVD film and vapor deposition formation, and controllability. be.

以上 出願人 セイコーエプソン株式会社that's all Applicant: Seiko Epson Corporation

Claims (3)

【特許請求の範囲】[Claims] (1)半導体ウェーハのイオン打込み処理時に半導体ウ
ェーハには超音波を印加する事を特徴とする半導体ウェ
ーハの処理方法。
(1) A method for processing a semiconductor wafer, which comprises applying ultrasonic waves to the semiconductor wafer during ion implantation processing of the semiconductor wafer.
(2)半導体ウェーハのドライエッチング処理時に半導
体ウェーハには超音波を印加する事を特徴とする半導体
ウェーハ処理方法。
(2) A semiconductor wafer processing method characterized by applying ultrasonic waves to the semiconductor wafer during dry etching processing of the semiconductor wafer.
(3)半導体ウェーハへのCVD膜形成時及び蒸着膜形
成時に半導体ウェーハ、あるいはガス・ソースあるいは
蒸着ソースには超音波を印加する事を特徴とする半導体
ウェーハの処理方法。
(3) A method for processing a semiconductor wafer, which comprises applying ultrasonic waves to the semiconductor wafer, gas source, or vapor deposition source during the formation of a CVD film or a vapor deposition film on the semiconductor wafer.
JP20768588A 1988-08-22 1988-08-22 Treatment of semiconductor wafer Pending JPH0256928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20768588A JPH0256928A (en) 1988-08-22 1988-08-22 Treatment of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20768588A JPH0256928A (en) 1988-08-22 1988-08-22 Treatment of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH0256928A true JPH0256928A (en) 1990-02-26

Family

ID=16543881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20768588A Pending JPH0256928A (en) 1988-08-22 1988-08-22 Treatment of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH0256928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6358823B1 (en) * 2000-04-12 2002-03-19 Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom
US7902091B2 (en) * 2008-08-13 2011-03-08 Varian Semiconductor Equipment Associates, Inc. Cleaving of substrates

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6358823B1 (en) * 2000-04-12 2002-03-19 Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom
US7902091B2 (en) * 2008-08-13 2011-03-08 Varian Semiconductor Equipment Associates, Inc. Cleaving of substrates
JP2012500132A (en) * 2008-08-13 2012-01-05 バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド Improved cleavage of the substrate

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