JPH0256693B2 - - Google Patents
Info
- Publication number
- JPH0256693B2 JPH0256693B2 JP56119701A JP11970181A JPH0256693B2 JP H0256693 B2 JPH0256693 B2 JP H0256693B2 JP 56119701 A JP56119701 A JP 56119701A JP 11970181 A JP11970181 A JP 11970181A JP H0256693 B2 JPH0256693 B2 JP H0256693B2
- Authority
- JP
- Japan
- Prior art keywords
- common bus
- memory
- cache memory
- data
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56119701A JPS5819970A (ja) | 1981-07-30 | 1981-07-30 | メモリアクセス制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56119701A JPS5819970A (ja) | 1981-07-30 | 1981-07-30 | メモリアクセス制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5819970A JPS5819970A (ja) | 1983-02-05 |
JPH0256693B2 true JPH0256693B2 (enrdf_load_stackoverflow) | 1990-11-30 |
Family
ID=14767932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56119701A Granted JPS5819970A (ja) | 1981-07-30 | 1981-07-30 | メモリアクセス制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5819970A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62109153A (ja) * | 1985-11-08 | 1987-05-20 | Fuji Facom Corp | デバイス装置 |
GB9008145D0 (en) * | 1989-05-31 | 1990-06-06 | Ibm | Microcomputer system employing address offset mechanism to increase the supported cache memory capacity |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50141938A (enrdf_load_stackoverflow) * | 1974-05-02 | 1975-11-15 |
-
1981
- 1981-07-30 JP JP56119701A patent/JPS5819970A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5819970A (ja) | 1983-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5276836A (en) | Data processing device with common memory connecting mechanism | |
US5644788A (en) | Burst transfers using an ascending or descending only burst ordering | |
JPH0256693B2 (enrdf_load_stackoverflow) | ||
JPH10178626A (ja) | 伝送装置及びサーバ装置並びに伝送方法 | |
US5546560A (en) | Device and method for reducing bus activity in a computer system having multiple bus-masters | |
US5790892A (en) | Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory | |
JPH04117538A (ja) | メモリ制御方式 | |
JPH035619B2 (enrdf_load_stackoverflow) | ||
JP2599184B2 (ja) | Dmacのリード転送制御装置 | |
JP3136681B2 (ja) | データ処理装置 | |
JPH08339353A (ja) | マルチプロセッサ装置 | |
JPS6232832B2 (enrdf_load_stackoverflow) | ||
JP2627355B2 (ja) | データ通信方式 | |
JPS58213371A (ja) | デ−タ処理システム | |
JPH0256692B2 (enrdf_load_stackoverflow) | ||
JPH0863396A (ja) | ディスクキャッシュ装置 | |
JPH07200526A (ja) | キャッシュメモリの初期化回路 | |
JP2588514Y2 (ja) | 通信制御装置 | |
JPS6213688B2 (enrdf_load_stackoverflow) | ||
JP2768022B2 (ja) | メモリコントローラ | |
JPS642985B2 (enrdf_load_stackoverflow) | ||
JPH0239342A (ja) | Ramディスクの記憶保全方式 | |
JPH03233780A (ja) | バスアクセス方式 | |
JPH10247162A (ja) | 電子計算機システム | |
JPH04267455A (ja) | マイクロコンピュータシステム |