JPH0256693B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control system in a microprocessor or the like.

In a processing system in which a processing unit, main memory, and cache memory are connected by an internal common bus, and input/output devices, etc. are connected by an external common bus, memory access requests issued from the processing unit and memory accesses issued from the external common bus are (DMA) requests. In the conventional system, when a DMA request occurs while a processing device is monopolizing the internal common bus, the DMA request is made to wait until the processing device finishes using the internal common bus.

The present invention was made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a memory access control method that improves system processing efficiency.

The present invention provides a first common bus, a second common bus connected to a processing device, a main storage device, and a cache memory, and a control bus connected to the first common bus and the second common bus. a processing system comprising: means for receiving a memory access request issued from the first common bus and outputting an access request signal to the cache memory; and receiving a permission signal from the processing device; means for writing data into the cache memory;
When it receives a memory write access request from the first common bus, it starts writing data from the first common bus to the main storage device, issues an access request signal to the cache memory to the processing device, and receives the permission signal. By receiving the
This is a memory access control method characterized by writing data into the cache memory.

Hereinafter, the present invention will be explained with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.
1 is a cache memory, 2 is a processor, 3 is an internal bus control unit, 4 is an internal bus, 5 is a common bus control unit,
6 is an external bus control unit, 7 and 8 are driver/receiver (D/R) units, 9 is a memory control unit, 10 is a memory, 11 is a common bus, 12 is an input/output device, A
is an I/O access request, B is a request signal, C is a permission signal, D, d are data, DMA is a DMA request,
R/W is a read/write command, and w is a write signal.
The cache memory 1 in the drawing includes a memory 10.
Some data d of the data in is stored,
By accessing this cache memory 1, the processor 2 can retrieve data d at high speed. Further, when the processor 2 needs to access the input/output device 12, it sends an I/O access request A and a read/write command R/
Emits a W.

In the drawing, processor 2 is cache memory 1.
When the common bus control unit 5 receives a DMA request DMA while accessing and reading data d, the external bus control unit 6 sends a write signal w to the D/R unit 8.
is issued to enable the D/R section 8, and the common bus 1 is activated.
Write data D from 1 to memory 10. In addition, when writing data D based on a DMA request, external bus control unit 6 determines whether it is also necessary to update data d in cache memory 2 (determined based on the address to which data D is written), If necessary, a request signal B is issued to the internal bus control section 3. The internal bus control unit 3 monitors the access of the processor 2 to the cache memory 1, and issues a permission signal C when the processor 2 finishes reading the data d. When the common bus control section 5 receives this permission signal C, it makes the D/R section 7 valid, so that writing of the data D to the cache memory 1 is started.

In the conventional method, processor 2 uses cache memory 1
Even if a DMA request (write) is generated from the common bus 11 side while accessing the memory 9, the writing to the memory 9 may have to wait. In the present invention, writing to the memory 9 is enabled, and writing to the cache memory 1 is performed depending on whether or not data in the cache memory 1 needs to be updated.This improves the processing efficiency of the system and the processing for DMA requests. It has the advantage of significantly increasing efficiency.

[Brief explanation of the drawing]

The drawing is a block diagram illustrating an embodiment of the present invention, and the symbols used in the drawing are as follows. 1 is a cache memory, 2 is a processor, 3 is an internal bus control unit, 4 is an internal bus, 5 is a common bus control unit, 6 is an external bus control unit, 7 and 8 are drivers/
Receiver (D/R) section, 9 is a memory control section, 1
0 is memory, 11 is common bus, 12 is input/output device, A is I/O access request, B is request signal, C
is a permission signal, D and d are data, DMA is a DMA request, R/W is a read/write command, and w is a write signal.

Claims (1)

[Claims] 1 a first common bus connected to input/output devices, etc.;
a second common bus connected to the processing device and the cache memory, a main storage device, and a control unit that controls connections between the first common bus, the second common bus, and the main storage device; In the processing system, when the control unit receives a memory write access request from the first common bus, it starts writing data from the first common bus to the main storage device, and the processing device 1. A memory access control system, wherein writing of data to said cache memory is executed by issuing an access request to said cache memory to said processing device and receiving a permission signal from said processing device.