JPS62109153A - Device equipment - Google Patents

Abstract

PURPOSE:To avoid the collision between internal buses by forming a device in a 2-stage hierarchical structure and providing an internal bus interface between the upper and lower internal buses. CONSTITUTION:In a normal mode, a bus interface 12 is kept open with connection secured between the upper and lower internal buses 9 and 10. Thus an external master device 3 and give access to both a register 6 and a LSi 8 with no consciousness of the difference between them. While the signal is sent to the interface 12 via a closing signal line 13 in such a case where the LSi 8 is started and DMA is carried out between the LSi 8 and a memory 7. Thus the interface 12 is closed. Under such conditions, the LSi 8 occupies the bus 10 to perform the DMA between said LSi 8 and the memory 7. While the device 3 can give access freely to the register 6 connected to the bus 9.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a device connected to a common bus, in which the internal bus of the device is duplicated so that it can be used without being aware of the duplication.

[Prior art and its problems]

FIG. 2 shows an example of the configuration of a conventional system with a single internal bus. 1 is a common bus, 2 is an internal bus, 3 is a master device connected to the common bus, 4 is an interface circuit for the common bus, 5 is a control circuit for priority use of the internal bus,
6 is a register, 7 is a memory, and 8 is an LSi. In such a configuration, for example, assume that the L S i 8 is activated and independently starts DMA with the memory 7. At this time, if the external master device 3 accesses the internal bus 2, a collision will occur on the internal bus, so the following two examples can be considered to prevent this. fl) Close the bus interface 4 and prohibit any access from the common bus 1. (2) The internal bus priority control circuit 5 allocates the right to use the internal bus to the external master device 3 and the LSi 8, and uses the internal bus alternately. However, when internal bus collisions are prevented by such a method, the following disadvantages occur. That is, flll
In this case, while the LSi 8 is in operation, it becomes impossible for the external mask device 3 to access the registers connected to the internal bus, and during that time, all operations for the device unit are stopped. In the case of (2), there is an interval between the operations of both the external master device 3 and LSt8, so if time monitoring is being performed, or if LSt8 is connected to an external input/output device and transmission is being performed between them. In some cases, the operation may not be done in time and a timeout may occur.

[Purpose of the invention]

An object of the present invention is to provide a device having an internal bus structure that prevents internal bus collisions when internal operations and external accesses are performed at the same time, and does not affect the access time of both. do.

[Key points of the invention]

In this invention, devices are layered into two levels, and an internal bus interface is provided between an internal bus in the upper layer and an internal bus in the lower layer. Normally, this internal interface is left open so that when it is accessed from the outside, only one bus interface is provided. When the mask connected to the lower layer internal bus accesses the memory etc. connected to the lower layer internal bus for DMA etc., this internal bus interface is closed. The lower layer internal bus performs DMA, and the registers connected to the upper layer internal bus can be accessed from an external master device in the same way as usual.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, where ■ is a common bus, 3 is an external master device connected to the common bus 1, 6 is a register, 7 is a memory, 8 is an LSt, and 9 is an upper layer. An internal bus 10 is a lower layer internal bus, 11 is an external bus interface that connects the external common bus 1 and the upper layer internal bus 9, and 12 is an internal bus that connects the upper layer internal bus 9 and the lower layer internal bus 10. interface, 13
is a signal line that closes the internal bus interface 12. In such a configuration, when the external master device 3 normally accesses the register 6 connected to the upper layer internal bus 9 or the LSt 8 connected to the lower layer internal bus 10, the internal bus interface 12 is in an open state and the upper layer Since the layer internal bus 9 and the lower layer internal bus 10 are in a coupled state, the register 6 connected to the upper layer internal bus 9 and the LSt 8 connected to the lower layer internal bus 10 can be used without being aware of the difference. Can be accessed. On the other hand, LSt8
When activated to perform DMA with the memory 7, a signal is simultaneously sent to the internal bus interface 12 via the closing signal line 13, and a gate (not shown) is sent to the internal bus interface 12. By closing the internal bus interface 12, the upper layer internal bus 9 and the lower layer internal bus 10 can be separated and operated individually. In this state, the LSt8 exclusively uses the lower layer internal bus 10 and performs DMA with the memory 7, and the external master device 3 can freely access the register 6 connected to the upper layer internal bus 9. .

【Effect of the invention】

According to the present invention, the internal bus is duplicated and can be used separately or combined to be used like a single tree bus, so even when the LS+ inside the device is operating independently. External masks are available. This is particularly effective in devices that require access in both DMA mode and program mode at the same time. Therefore, for example 1
If this method is adopted when designing cards, DM
Since other registers can be accessed even during A, parallel operation of DMA and program mode processing is possible without placing a burden on the software, and the benefits obtained from this (multi-processing effect) are extremely large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a device according to the present invention, and FIG. 2 is a block diagram of a conventional device. 1: Common bus, 2: Internal bus, 3: External master device, 4: Bus interface, 5: Internal bus priority control circuit + 6: Register, 7: Memory. 8: LSi, 9: Upper layer internal bus, 10: Lower layer internal bus, 11: External bus interface, 12: Internal bus interface, 13: Closing signal line. Marurijinshu nr J Koro 1 ”f7+

Claims (1)

[Claims] 1) An upper layer internal bus is connected to a common bus via an external bus interface, and a lower layer internal bus is connected to the upper layer internal bus via an internal bus interface, and the internal bus interface is normally A device apparatus characterized in that it is opened and closed during a period when a master device connected to the lower layer internal bus accesses a memory or the like connected to the lower layer internal bus.