JPS6022264A - Data processor - Google Patents

Abstract

PURPOSE:To improve an entire processing speed by dividing the memory space of a main microprocessor so as to use in common a divided space with each slave microprocessor thereby conducting easy and quick data transfer between both. CONSTITUTION:A single main microprocessor 10 is provided to a data processor and an input/output port 11 and a control circuit 12 mediating the right of use and dividing the memory space are connected to the processor 10. An exclusive memory 13 and tri-state buffers 14, 17 switching the bus line are connected to the processor 10 via a bus line. Then the slave microprocessors 15, 18 and shared memories 16, 19 are connected to the buffers 14, 17, and the control circuit 12 is connected to the buffers 14, 17, and the microprocessors 15, 18. Thus, the memory space of the processor 10 is divided and the memories 16, 19 are shared with the slave processors 15, 18 and the processor 10 so as to improve the processing speed of the entire processor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data collection system, a data analysis system,
The present invention relates to data processing devices using other microprocessors.

Configuration of conventional examples and their problems In recent years, data processing devices using microprocessors have been used in a wide range of fields, and it is not uncommon for them to be used to process large amounts of data.

In such cases, it is often not possible to obtain sufficient processing speed with a single microprocessor, and it has become common to use multiple microprocessors to configure a data processing device as a so-called multiprocessor system. ing.

FIG. 1 shows the configuration of a conventional data processing device using such a plurality of microprocessors.
1 is a data processing microprocessor, 2 is a memory dedicated to the data processing microprocessor, 3 is an input/output microprocessor, 4 is a memory dedicated to the input/output microprocessor, and 6 is an input to the data processing microprocessor 1. Output microprocessor 3f: input/output port for connection; 6 is an input/output port for input/output with external equipment.

Regarding the conventional data processing device configured as described above,
Let's explain its operation. First, data from an external device is input to the input/output microprocessor sensor 3 through the input/output capotro, where it undergoes preprocessing such as changing the data format, and then is processed through the input/output port 5 for connection. The data is sent to the microprocessor 1 for necessary processing. The processed data is sent from the data processing microprocessor 1 to the input/output microprocessor 3 via the connection input/output capotro, and after undergoing necessary post-processing, is sent to the external device via the input/output capotro. Output.

However, in the conventional configuration described above, the two microprocessors are connected through input/output ports, so there is a limit to the data transfer speed, so even if the number of microprocessors is increased, the overall processing speed will be slow. No improvement,
Further, there were other problems such as the hardware becoming larger and the program becoming more complex.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems.It is a data processing system that can be realized with small hardware, can be used with a simple program, has flexible expandability, and can easily improve processing speed. The purpose is to provide processing equipment.

Structure of the Invention The present invention consists of a plurality of slave microprocessors that are in charge of actual data processing, and a single master processor that is responsible for inputting and outputting data to and from the outside and distributing and collecting these input and output data to each slave microprocessor. It is a data processing device equipped with a microprocessor and a control circuit that divides memory space and arbitrates usage rights.By dividing the memory space of the main microprocessor and sharing it with each subordinate microprocessor, it is possible to Data transfer can be performed easily and at high speed, and the overall processing speed can be greatly improved.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows the configuration of a data processing device in an embodiment of the present invention, in which 1o is a main microprocessor;
11 is an input/output port that performs input/output with external equipment; 12 is a control circuit that divides memory space and arbitrates usage rights; 1
3 is a memory dedicated to the main microprocessor, 14 is a three-state buffer for switching buses, 16 is a subordinate microprocessor, and 16 is a shared memory. The 3-state buffer 17 and the shared memory of the 18 subordinate microprocessors 19 are equivalent to those of 14, 15, and 16, respectively.

FIG. 3 shows the details of the configuration of the control circuit 12 and the connections with each microprocessor, where 2° indicates the opening of the address from the upper address of the main microprocessor 9 to each subordinate microprocessor 15.18. 21 is a selector circuit for selecting a bus release acceptance signal for each subordinate microprocessor; 22 is a selector circuit for providing a start signal to each subordinate microprocessor and checking whether each subordinate microprocessor has finished processing; This is a control port circuit for

The operation of the data processing device in this embodiment configured as above will be explained below according to the flowchart shown in FIG. 4. Figure 4) is a processing flowchart of the main microprocessor 10, and 3 is a processing flowchart of the microprocessor 18. first,
Data input from an external device through the input/output port 11 is stored in the first shared memory 16 by the main microprocessor 1o. At this time, the main microprocessor 9
attempts to access the first shared memory 16, the first subordinate microprocessor 16 from its upper address
A bus release request signal is generated by the decoder circuit 2o and applied to the first slave microprocessor 15. When the first slave microprocessor 16 receives the bus release request, it sends an acceptance signal to the main microprocessor 10 through the selector circuit 21. With this acceptance signal,
The three-state buffer 14 is opened, and at the same time the main microprocessor 10 is released from standby and the shared memory 16 is opened.
You will have access to. When the data storage is completed, the main microprocessor 1o transfers the data to the first shared memory 1.
6 is no longer accessed, the bus release request from the decoder circuit 20 is no longer issued, and the first shared memory 16 is therefore connected to the first subordinate microprocessor 15. Next, the first slave microprocessor 1 is transferred from the main microprocessor 10i/C through the control port 22.
6, an interrupt request is issued, which activates the subordinate microprocessor 15 and starts processing. Data is similarly stored in the second shared memory 19, and the second subordinate processor 18 is activated to start processing. When activated, the dependent processors 16 and 18 process data on the shared memory, and when the processing is completed, they stop, and a halt signal indicating this is output. The main microprocessor 1゜ checks this halt signal through the control port 22, and when it confirms the completion of processing, it retrieves the result from the shared memory lJ1.6.19 using the same operation as when storing, and outputs it to the external device through the input/output port 11. I will do it.

FIG. 5 shows the memory space of the main microprocessor 10 and the slave microprocessor 15, when the capacity of the memory 13 and the shared memory I716, 19 is 8 KB each.
18, addresses 2000H to 3FFFH of the main microprocessor 10 are shared as the first shared memory with addresses 0000) (~1FFFH) of the first subordinate microprocessor, and similarly 4000H ~5FFFH address is the second shared memory, and the second slave microprocessor's address is 0OOOH~1F.
It will be shared with FFH1 land. However, here H is 1
This is a subscript indicating a hexadecimal number.

As described above, according to this embodiment, the control circuit composed of the decoder circuit 20° selector circuit 21 and the control port 22 has an extremely simple configuration and can perform all the processes as many as the number of subordinate microprocessors in parallel and at high speed. can be set.

Although this embodiment shows a case in which there are two subordinate microprocessors, any number of subordinate microprocessors can be easily added by forming a set of three (3-state buffer, shared memory, and subordinate microprocessors).

In addition, the flowchart in Figure 4 shows a method of sequentially distributing data to each subordinate microprocessor.
It goes without saying that more dynamic processing may be performed using interrupts or the like.

Effects of the Invention The present invention transfers data between a plurality of slave microprocessors and a single master microprocessor by dividing the memory space of the master microprocessor and sharing the memory space of each slave microprocessor. As a result, the transfer time, which was a bottleneck in conventional methods, can be significantly reduced, and since the same number of processes as the subordinate microprocessors can be performed in parallel, the overall processing speed can be greatly improved. The program only needs to be extremely simple, and an excellent data processing device with flexible expandability can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional data processing device, FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 3 is a detailed diagram of each microprocessor and control circuit in FIG. 4(-) and 4(b) are flowcharts showing the operation of the data processing apparatus, and FIG. 5 is a memory map showing the interrelationship of its memory spaces. 1...Microprocessor for data processing, 2.
...Memory, 3...Microprocessor for input/output, 4...Memory, 5...I/O port for connection, 6...Input/output Port, 1o...
... Main microprocessor, 11 ... Input/output port, 12 ... Control circuit, 13 ...
・Memory, 14...3-state buffer, 16
...First slave microprocessor, 16...
...First shared memory, 17... Three-state buffer, 18... Second subordinate microprocessor, 19... Second shared memory, 20・・・
... Decoder circuit, 21 ... Selector circuit, 22 ... Control port. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure (oL) ('b) Figure 5

Claims (1)

[Claims] A single main microprocessor, a plurality of subordinate microprocessors, an input/output unit connected to the main microprocessor, and a memory space of the main microprocessor that is divided into memory spaces of each of the subordinate microprocessors. and arbitration means for causing the subordinate processor to relinquish the right to use the memory space only when the main microprocessor attempts to access the memory space shared with one of the subordinate processors. A data processing device.