JPH0253965B2 - - Google Patents
Info
- Publication number
- JPH0253965B2 JPH0253965B2 JP54169064A JP16906479A JPH0253965B2 JP H0253965 B2 JPH0253965 B2 JP H0253965B2 JP 54169064 A JP54169064 A JP 54169064A JP 16906479 A JP16906479 A JP 16906479A JP H0253965 B2 JPH0253965 B2 JP H0253965B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- transistors
- transistor pair
- input terminal
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007562 laser obscuration time method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
Landscapes
- Static Random-Access Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16906479A JPS5691526A (en) | 1979-12-25 | 1979-12-25 | Flip-flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16906479A JPS5691526A (en) | 1979-12-25 | 1979-12-25 | Flip-flop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5691526A JPS5691526A (en) | 1981-07-24 |
| JPH0253965B2 true JPH0253965B2 (zh) | 1990-11-20 |
Family
ID=15879662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16906479A Granted JPS5691526A (en) | 1979-12-25 | 1979-12-25 | Flip-flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5691526A (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04118448U (ja) * | 1991-03-28 | 1992-10-22 | オリンパス光学工業株式会社 | 反転蒸着装置 |
-
1979
- 1979-12-25 JP JP16906479A patent/JPS5691526A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04118448U (ja) * | 1991-03-28 | 1992-10-22 | オリンパス光学工業株式会社 | 反転蒸着装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5691526A (en) | 1981-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100292595B1 (ko) | 저 전력 및 작은 영역의 슬립 모드를 갖는 반도체 집적 회로 | |
| KR970010642B1 (ko) | 반도체 장치 | |
| TWI625939B (zh) | electronic circuit | |
| KR950002077B1 (ko) | 출력 전압 레벨을 임시로 시프트하는 고속 출력 버퍼 장치 | |
| US6958948B2 (en) | Semiconductor device having a data latching or storing function | |
| KR100999213B1 (ko) | 저 누설 및 데이터 보유 회로소자 | |
| JPH0973784A (ja) | 半導体装置及びその制御回路 | |
| JPH11112297A (ja) | ラッチ回路及びこのラッチ回路を有する半導体集積回路 | |
| JP2000013215A (ja) | 半導体集積回路 | |
| JPH0786916A (ja) | 半導体集積回路 | |
| KR910003593B1 (ko) | 고집적도 메모리용 모드 선택회로 | |
| US6621306B2 (en) | Random logic circuit | |
| JP3686174B2 (ja) | 半導体集積回路装置 | |
| TWI708245B (zh) | 整合式位準轉換器 | |
| JPH0249519B2 (zh) | ||
| US4004170A (en) | MOSFET latching driver | |
| JP2771375B2 (ja) | レベルシフト回路 | |
| JPS6051023A (ja) | 論理レベル変換回路 | |
| EP1166444A1 (en) | Electronic digital circuit operable active mode and sleep mode | |
| JPH0253965B2 (zh) | ||
| JP3255159B2 (ja) | 半導体集積回路 | |
| JP3500598B2 (ja) | ラッチ回路 | |
| JPH05102312A (ja) | 半導体集積回路 | |
| JPS5926134B2 (ja) | ラツチ回路 | |
| JP3255158B2 (ja) | 半導体集積回路 |