JPH0251259B2 - - Google Patents
Info
- Publication number
- JPH0251259B2 JPH0251259B2 JP59017950A JP1795084A JPH0251259B2 JP H0251259 B2 JPH0251259 B2 JP H0251259B2 JP 59017950 A JP59017950 A JP 59017950A JP 1795084 A JP1795084 A JP 1795084A JP H0251259 B2 JPH0251259 B2 JP H0251259B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- channel stopper
- insulating film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
- H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59017950A JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59017950A JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49139096A Division JPS5947471B2 (ja) | 1974-12-03 | 1974-12-03 | 絶縁ゲ−ト型電界効果半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59188142A JPS59188142A (ja) | 1984-10-25 |
| JPH0251259B2 true JPH0251259B2 (enExample) | 1990-11-06 |
Family
ID=11958040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59017950A Granted JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59188142A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2644275B2 (ja) * | 1988-05-11 | 1997-08-25 | 富士通株式会社 | 半導体装置の製造方法 |
-
1984
- 1984-02-03 JP JP59017950A patent/JPS59188142A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59188142A (ja) | 1984-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4041518A (en) | MIS semiconductor device and method of manufacturing the same | |
| US6518623B1 (en) | Semiconductor device having a buried-channel MOS structure | |
| US4285116A (en) | Method of manufacturing high voltage MIS type semiconductor device | |
| US5030584A (en) | Method for fabricating MOS semiconductor device operable in a high voltage range using polysilicon outdiffusion | |
| KR880006781A (ko) | 반도체 집적회로 및 그 제조방법 | |
| KR890013796A (ko) | 반도체장치 및 그 제조방법 | |
| US5242849A (en) | Method for the fabrication of MOS devices | |
| JPS61194777A (ja) | 半導体集積回路装置 | |
| JPS5947471B2 (ja) | 絶縁ゲ−ト型電界効果半導体装置の製造方法 | |
| US4786961A (en) | Bipolar transistor with transient suppressor | |
| JPH02178965A (ja) | 絶縁分離型電界効果半導体装置 | |
| JPS63194367A (ja) | 半導体装置 | |
| US4011653A (en) | Method for manufacturing a semiconductor integrated circuit including an insulating gate type semiconductor transistor | |
| JPH0251259B2 (enExample) | ||
| JP2547729B2 (ja) | 高耐圧パワ−集積回路 | |
| JPS62262462A (ja) | 半導体装置 | |
| JPH05114734A (ja) | 半導体装置 | |
| JPH067556B2 (ja) | Mis型半導体装置 | |
| US5279979A (en) | Semiconductor having diffusion region separated from the gap electrode and wiring layer | |
| JP2629426B2 (ja) | 2重拡散型misfetを備えた半導体装置及びその製造方法 | |
| JPH04127574A (ja) | 縦型絶縁ゲート電界効果トランジスタ | |
| JPS5898969A (ja) | 半導体装置 | |
| JPS6146062A (ja) | ラテラルトランジスタ半導体装置の製造方法 | |
| JPS61150376A (ja) | 半導体装置 | |
| JP2710356B2 (ja) | 半導体装置 |