JPH0251259B2 - - Google Patents
Info
- Publication number
- JPH0251259B2 JPH0251259B2 JP59017950A JP1795084A JPH0251259B2 JP H0251259 B2 JPH0251259 B2 JP H0251259B2 JP 59017950 A JP59017950 A JP 59017950A JP 1795084 A JP1795084 A JP 1795084A JP H0251259 B2 JPH0251259 B2 JP H0251259B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- channel stopper
- insulating film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59017950A JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59017950A JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49139096A Division JPS5947471B2 (ja) | 1974-12-03 | 1974-12-03 | 絶縁ゲ−ト型電界効果半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59188142A JPS59188142A (ja) | 1984-10-25 |
| JPH0251259B2 true JPH0251259B2 (enrdf_load_stackoverflow) | 1990-11-06 |
Family
ID=11958040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59017950A Granted JPS59188142A (ja) | 1984-02-03 | 1984-02-03 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59188142A (enrdf_load_stackoverflow) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2644275B2 (ja) * | 1988-05-11 | 1997-08-25 | 富士通株式会社 | 半導体装置の製造方法 |
-
1984
- 1984-02-03 JP JP59017950A patent/JPS59188142A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59188142A (ja) | 1984-10-25 |
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