JPH024937B2 - - Google Patents
Info
- Publication number
- JPH024937B2 JPH024937B2 JP8657682A JP8657682A JPH024937B2 JP H024937 B2 JPH024937 B2 JP H024937B2 JP 8657682 A JP8657682 A JP 8657682A JP 8657682 A JP8657682 A JP 8657682A JP H024937 B2 JPH024937 B2 JP H024937B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- bus
- memory
- common
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8657682A JPS58203568A (ja) | 1982-05-24 | 1982-05-24 | マルチプロセツサシステム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8657682A JPS58203568A (ja) | 1982-05-24 | 1982-05-24 | マルチプロセツサシステム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58203568A JPS58203568A (ja) | 1983-11-28 |
| JPH024937B2 true JPH024937B2 (enrdf_load_stackoverflow) | 1990-01-31 |
Family
ID=13890829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8657682A Granted JPS58203568A (ja) | 1982-05-24 | 1982-05-24 | マルチプロセツサシステム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58203568A (enrdf_load_stackoverflow) |
-
1982
- 1982-05-24 JP JP8657682A patent/JPS58203568A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58203568A (ja) | 1983-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0511674B1 (en) | Single chip microcomputer | |
| EP0099125B1 (en) | Multicomputer system having dual common memories | |
| JPS58134360A (ja) | デ−タ処理サブシステム | |
| JPH04246745A (ja) | 情報処理装置及びその方法 | |
| EP0522582A2 (en) | Memory sharing for communication between processors | |
| US5754802A (en) | Increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation | |
| JPH024937B2 (enrdf_load_stackoverflow) | ||
| JPH01125644A (ja) | データ転送装置 | |
| JPH07271654A (ja) | コントローラ | |
| JPS6259825B2 (enrdf_load_stackoverflow) | ||
| JPS59165287A (ja) | 情報処理システム | |
| JPS6337419B2 (enrdf_load_stackoverflow) | ||
| JPS60254267A (ja) | デ−タ転送方式 | |
| JPS61211759A (ja) | マルチcpuシステムにおける2ポ−トメモリ制御回路 | |
| EP1990725B1 (en) | Central processing unit, central processing unit control method, and information processing system | |
| JPS5835635A (ja) | メモリ制御回路 | |
| JPH07234845A (ja) | 並列計算機における入出力用セルおよび並列計算機システム | |
| JPS6126164A (ja) | デ−タ転送制御方法 | |
| JPH0148574B2 (enrdf_load_stackoverflow) | ||
| JPS60142450A (ja) | 記憶システム | |
| JPS6218074B2 (enrdf_load_stackoverflow) | ||
| JP3219422B2 (ja) | キャッシュメモリ制御方式 | |
| JP3246736B2 (ja) | 計算機システム | |
| JPS58211269A (ja) | マルチプロセツサシステム | |
| JPS61273659A (ja) | デ−タ処理方式 |