JPH0249061B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting circuit for a semiconductor integrated circuit that is integrated within a single semiconductor substrate.

A muting circuit having a circuit configuration as shown in FIG. 1 is known as a muting circuit having a function of attenuating the amplitude of a signal appearing at a signal output terminal as necessary.

In the circuit shown in FIG. 1, the input signal S _I applied to the input terminal 2 attached to the base of the signal amplification transistor 1 is amplified by the signal amplification transistor 1, and the muting circuit section 3 does not operate.
When the muting transistor 4 is in the off state, the resistor 6 is driven through the coupling capacitor 5, and a signal S _A centered on the potential of the earth point E appears at the output terminal 7. On the other hand, when applying mutating, the muting circuit section 3
Transistor 8 inside is turned off. When the transistor 8 is suddenly disconnected, the collector resistor 10 of the transistor 8 and the diode 1 are connected from the power supply terminal 9.
1, a current is injected into the emitter of the PNP transistor 12, and the collector current flows to the base of the mutating transistor 4, making the mutating transistor 4 conductive. As a result,
A part of the signal flowing to the output terminal 7 flows to the muting transistor 4, and the amplitude of the signal flowing to the output terminal 7 is attenuated. In addition, in the figure, 13
and 14 are the collector resistance and emitter resistance of the signal amplification transistor 1.

By the way, the illustrated muting circuit section 3
When integrated into a single semiconductor substrate using the well-known NPN planar process, the structure will be as shown in the cross-sectional view of Figure 2. That is, the second
The figure shows a horizontal PNP transistor 12 and a vertical NPN transistor 4 among the circuit elements of the muting circuit section 3 shown in FIG. The isolation region 18, the P-type region 19, and the N-type region 20 are formed by a well-known NPN planar process. As a result, as is well known, the mutating transistor 4 has a parasitic diode 15 formed by an isolation PN junction formed between the N-type collector region 17 and the P-type semiconductor substrate 16. Become.
This creates the problem of signal amplitude clipping. That is, in a typical bipolar integrated circuit, the starting material is silicon, so the parasitic diode 15 has a forward voltage drop of approximately 0.7 volts as a silicon diode.
Therefore, during the negative half cycle of the signal when this parasitic diode 15 is forward biased, its voltage decreases.
When it reaches 0.7 volts, this parasitic diode 15
becomes conductive, and the amplitude of the signal appearing at the output terminal 7 is clipped to a potential level about 0.7 volts negative than the ground potential (0 volts), and even if the muting transistor 4 is in the off state, the output signal is distorted. is brought about.

The present invention deals with signal distortion caused by the presence of parasitic diodes when the muting circuit section of the circuit configuration shown in FIG. This was done to eliminate this problem, and the connection relationship of the muting transistor connected between the output terminal of the signal output circuit and the ground point is reversed from the circuit shown in Figure 1, that is, the emitter is connected to the signal output terminal. It is connected to the output terminal of the output circuit, and the collector is connected to the ground point.

The present invention will be explained in detail below with reference to FIG.

FIG. 3 is a diagram showing a muting circuit for a semiconductor integrated circuit according to the present invention, which is the same as the circuit shown in FIG. 1 except for the connection of the muting transistor 4 to the circuit. The connecting relationship of the input transistor 4 to the circuit is such that its emitter is connected to the output terminal 7 and its collector is connected to the ground point. If the muting circuit section 3 with such circuit connections is made into a semiconductor integrated circuit, it will have a structure as shown in the cross-sectional view of FIG. 4. As will be seen, the mutating transistor 4 has its collector 17
is connected to the semiconductor substrate 16 by a wiring 21,
Since the N-type region 20 of the emitter is independent from the semiconductor substrate 16 via the P-type region 19 of the base, no parasitic diode exists at the emitter terminal. Therefore, the problem of signal clipping due to the parasitic diode 15 as in the circuit shown in FIG. 1 does not occur. In this circuit, the effect of clipping the signal amplitude is achieved because the amplitude of the signal at the output terminal 7 is lower than the base potential (0 volts) at PNP.
Collector-base breakdown voltage of type transistor 12
If the voltage is negative by the sum of BV _CB12 and the base-emitter forward voltage V _BE4 of the mutating transistor 4, and the collector-base forward voltage of the PNP transistor 12 is lower than the ground potential.
This is limited to the case where the voltage is positive by the sum of V _CB12 and the emitter-base breakdown voltage BV _EB4 of the muting transistor 4. That is, in the negative half cycle of the output signal, the collector-base junction of the PNP transistor 12 is reverse biased.
The amplitude of the signal S _A appearing at output terminal 7 is |V _BE4
When +BV _CB12 | is reached, the PNP transistor 12 breaks down and a signal amplitude clipping effect occurs. Furthermore, in the positive half cycle, the emitter-base junction of the muting transistor 4 is reverse biased, and when the amplitude of the signal S _A reaches |BV _BE4 +V _CB12 |, the muting transistor 4 breaks down and the same occurs. A clipping effect on the signal amplitude occurs.

By the way, using a silicon substrate as a starting material,
The emitter-base breakdown voltage BV _EB (NPN) of a vertical NPN transistor in a bipolar integrated circuit formed by the NPN planar process is usually 5 volts or more, and the collector-base breakdown voltage BV _CB (PNP) of a lateral PNP transistor is usually 15 volts or more. More than a bolt. Therefore, no clipping occurs unless the signal amplitude about the ground potential reaches a large amplitude of 10 volts (p-p) or more. Normally, the amplitude of the output signal of a muting circuit is on the order of 6 volts (p-p) at most, so if the muting circuit of the present invention is used, the disadvantage of distortion in the output signal no longer occurs.

That is, the use of the lateral PNP transistor 12 ensures that the muting operation is performed without causing distortion to the output signal even during negative half cycles.

By the way, if the muting transistor of the present invention is a transistor with a general vertical structure,
Since the emitter area is significantly smaller than the collector area, the current amplification factor β _R under the usage condition where the collector is grounded and the emitter is connected to the output terminal is
This is smaller than the current amplification factor β _F under normal operating conditions when the emitter is grounded. For example, if a common-emitter transistor with a current amplification factor β _F of about 100 is used as a muting transistor, the current amplification factor β _R under the usage conditions of the present invention is 2.
It decreases to about 3.

In order to perform a reliable muting operation under the usage conditions of such a transistor, a resistor 1 is required.
0 to the emitter of transistor 12, but since this resistor 10 is also the collector resistance of transistor 8, its value cannot be changed simply for the purpose of increasing the injected current. . Therefore, when integrating the muting circuit of the present invention into a semiconductor integrated circuit, if the structure of the muting transistor 4 is such that the emitter area is as close to the collector area as possible, even under the condition of use where the collector is grounded, It becomes possible to significantly improve the current amplification factor, and there is no need to intentionally change the value of the resistor 10.

FIG. 5 shows the muting transistor 4 in the muting circuit having the configuration shown in FIG.
I _E −V _CB and I _E −V _EB during saturated operation of
It is a characteristic diagram showing the characteristics, and the emitter base voltage V _EB is larger than the collector base voltage V _CB at the same emitter current. Therefore, the remaining collector-emitter voltage V _CE becomes the difference between the output terminal 7 and the ground point, and this becomes the potential difference between when muting is applied and when no muting is applied, and the problem that occurs as a shock sound in the speaker is solved. It cannot be excluded. On the other hand, in the muting circuit for semiconductor integrated circuits of the present invention, the magnitude relationship between V _CB and V _EB shown in FIG. 3 is reversed, but when the emitter area of the muting transistor is made close to the collector area as described above, , the difference between V _EB and V _CB becomes extremely small, and the potentials of the output terminal 7 and the ground point approach almost the same potential. Therefore, the shock based on the potential difference between when muting is applied and when not Sound generation is suppressed.

By the way, lateral structure transistors are known as transistors in which the emitter area is close to the collector area, but the current amplification factor β _F of the emitter grounded and the current amplification factor β _R of the collector grounded transistor of the lateral structure transistor are both extremely low. This is a small value, and the absolute value of the current amplification factor β _R cannot be increased. In addition, reverse transistors are also known, but the difference between current amplification factor β _F and β _R is large and current amplification factor β _R is small. However, even in this case, the current amplification factor β _R of the common collector can be improved by increasing the emitter area. That is, it is important in the present invention to make the emitter area of the vertically structured transistor as large as possible so that the emitter area approaches the collector area.

As is clear from the above explanation, when the muting circuit for a semiconductor integrated circuit of the present invention is made into a semiconductor integrated circuit, the collector of the muting transistor is grounded, that is, connected to the semiconductor substrate. A parasitic diode no longer exists in the collector, and the influence of the parasitic diode can be eliminated. Furthermore, by making the emitter area as close as possible to the collector area when building the muting transistor, the potential difference between when muting is applied and when it is not applied is reduced, and the shock noise is effectively suppressed.

In addition, although the above explanation illustrated the case where the ground potential is 0 volts, it goes without saying that this may be used as a specific reference potential.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram for explaining the configuration and operation of a known muting circuit, Fig. 2 is a sectional view of the main part when it is made into a semiconductor integrated circuit, and Fig. 3 is a semiconductor of the present invention. A circuit diagram for explaining the configuration and operation of a muting circuit for integrated circuits, FIG. 4 is a cross-sectional view of the main part of the semiconductor integrated circuit, and FIG. 5 is a diagram showing the circuit shown in FIG. 1 during saturation operation of the muting transistor. in
FIG. 3 is a characteristic diagram showing I _E −V _CB and I _E −V _EB characteristics. DESCRIPTION OF SYMBOLS 1... Signal amplification transistor, 2... Input terminal, 3... Muting circuit section, 4... Muting transistor, 5... Coupling transistor, 6... Load, 7... Output terminal, 8... Switching Transistor, 9... Power supply terminal, 10...
Collector resistance, 11...Diode, 12...
PNP type transistor, 14...emitter resistor,
15... Parasitic diode.

Claims (1)

[Claims] 1. One end of a load is connected to the signal source via a coupling capacitor, an output terminal is attached to a connection point between the load and the coupling capacitor, and the other end of the load is connected to a predetermined reference potential point. A switching transistor whose emitter is connected to the output terminal of the output circuit and whose collector is connected to the reference potential point is integrated into a semiconductor substrate as a vertical NPN transistor of a bipolar integrated circuit formed by an NPN planar process. At the same time, a current supply circuit connected to the base of the switching transistor and supplying an operating current is integrally integrated into the semiconductor substrate, and furthermore, a current supply circuit is connected to the base of the switching transistor and supplies an operating current.
A muting circuit for a semiconductor integrated circuit, characterized in that the junction area is selected to be close to the collector-base PN junction area.