JPH0243214B2 - - Google Patents
Info
- Publication number
- JPH0243214B2 JPH0243214B2 JP19442982A JP19442982A JPH0243214B2 JP H0243214 B2 JPH0243214 B2 JP H0243214B2 JP 19442982 A JP19442982 A JP 19442982A JP 19442982 A JP19442982 A JP 19442982A JP H0243214 B2 JPH0243214 B2 JP H0243214B2
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- access request
- memory
- buffer means
- registered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19442982A JPS5983256A (ja) | 1982-11-05 | 1982-11-05 | メモリ制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19442982A JPS5983256A (ja) | 1982-11-05 | 1982-11-05 | メモリ制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5983256A JPS5983256A (ja) | 1984-05-14 |
| JPH0243214B2 true JPH0243214B2 (enExample) | 1990-09-27 |
Family
ID=16324448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19442982A Granted JPS5983256A (ja) | 1982-11-05 | 1982-11-05 | メモリ制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5983256A (enExample) |
-
1982
- 1982-11-05 JP JP19442982A patent/JPS5983256A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5983256A (ja) | 1984-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9361236B2 (en) | Handling write requests for a data array | |
| US8954681B1 (en) | Multi-stage command processing pipeline and method for shared cache access | |
| JPS61109146A (ja) | 先行制御方式 | |
| US5603006A (en) | Cache control unit using a plurality of request stacks | |
| CN112506823A (zh) | 一种fpga数据读写方法、装置、设备及可读存储介质 | |
| US7111127B2 (en) | System for supporting unlimited consecutive data stores into a cache memory | |
| US4648033A (en) | Look-aside buffer LRU marker controller | |
| CA1116756A (en) | Cache memory command circuit | |
| JPH0243214B2 (enExample) | ||
| US6349370B1 (en) | Multiple bus shared memory parallel processor and processing method | |
| US6904500B2 (en) | Cache controller | |
| JPH05282208A (ja) | キャッシュメモリ制御方式 | |
| JPH0551933B2 (enExample) | ||
| US6279082B1 (en) | System and method for efficient use of cache to improve access to memory of page type | |
| GB2037466A (en) | Computer with cache memory | |
| JPS61217834A (ja) | デ−タ処理装置 | |
| JPS59214977A (ja) | デ−タ処理装置 | |
| JPH05120133A (ja) | キヤツシユ装置 | |
| JPH07152649A (ja) | メモリキャッシング方法及び装置 | |
| JPH02176839A (ja) | 情報処理装置 | |
| JPS63187349A (ja) | 記憶装置 | |
| JPH086853A (ja) | 記憶制御方法 | |
| JP2003122632A (ja) | キャッシュデータ登録システム及び登録方法 | |
| JPH04288647A (ja) | キャッシュメモリにおける置き換え制御装置 | |
| JPH02259945A (ja) | ストア処理方式 |