JPH0241070B2 - - Google Patents

Info

Publication number
JPH0241070B2
JPH0241070B2 JP56122024A JP12202481A JPH0241070B2 JP H0241070 B2 JPH0241070 B2 JP H0241070B2 JP 56122024 A JP56122024 A JP 56122024A JP 12202481 A JP12202481 A JP 12202481A JP H0241070 B2 JPH0241070 B2 JP H0241070B2
Authority
JP
Japan
Prior art keywords
mask
bit
bits
array
vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56122024A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5822446A (ja
Inventor
Hitoshi Abe
Shigeo Nagashima
Koichiro Omoda
Hiroshi Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56122024A priority Critical patent/JPS5822446A/ja
Publication of JPS5822446A publication Critical patent/JPS5822446A/ja
Publication of JPH0241070B2 publication Critical patent/JPH0241070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
JP56122024A 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式 Granted JPS5822446A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56122024A JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56122024A JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Publications (2)

Publication Number Publication Date
JPS5822446A JPS5822446A (ja) 1983-02-09
JPH0241070B2 true JPH0241070B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-09-14

Family

ID=14825693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56122024A Granted JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Country Status (1)

Country Link
JP (1) JPS5822446A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62276668A (ja) * 1985-07-31 1987-12-01 Nec Corp ベクトルマスク演算制御ユニツト
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5737885B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-12-22 1982-08-12
JPS6042983B2 (ja) * 1979-11-09 1985-09-26 富士通株式会社 命令制御方式

Also Published As

Publication number Publication date
JPS5822446A (ja) 1983-02-09

Similar Documents

Publication Publication Date Title
JPH0248931B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2889845B2 (ja) 情報処理装置
EP0113398B1 (en) Indexed-indirect addressing method using prefix codes in a data processor
JPH0786826B2 (ja) 整数除算回路
US4028670A (en) Fetch instruction for operand address calculation
JPH034936B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US6230238B1 (en) Method and apparatus for accessing misaligned data from memory in an efficient manner
JPH0241070B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2703884B2 (ja) データ書込み制御方式
US4212058A (en) Computer store mechanism
JPH0831033B2 (ja) データ処理装置
JPH0544049B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0795269B2 (ja) 命令コードのデコード装置
JPS59184943A (ja) 情報処理装置
JPS6017131B2 (ja) メモリ制御回路
JPS6212532B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP2671161B2 (ja) レジスタ干渉チェック方式
JPS61110247A (ja) 記憶装置
JPS6320631A (ja) レジスタ選択方式
JPS60218146A (ja) 記憶装置アドレス制御方式
JPH05250156A (ja) Ｒｉｓｃプロセッサ
JPS59129995A (ja) 記憶装置
JPS62210541A (ja) レジスタ選択方式
JPH03119431A (ja) エラー検出抑止回路
JPH02288975A (ja) ベクトル演算装置