JPH023943A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH023943A
JPH023943A JP63152811A JP15281188A JPH023943A JP H023943 A JPH023943 A JP H023943A JP 63152811 A JP63152811 A JP 63152811A JP 15281188 A JP15281188 A JP 15281188A JP H023943 A JPH023943 A JP H023943A
Authority
JP
Japan
Prior art keywords
integrated circuit
metal wiring
bonding pad
pad part
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63152811A
Other languages
Japanese (ja)
Inventor
Ichiro Kitao
北尾　一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63152811A priority Critical patent/JPH023943A/en
Publication of JPH023943A publication Critical patent/JPH023943A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the disconnection of metal wiring by forming a bonding pad part newly and largely. CONSTITUTION:On metal wiring 2 of an element protecting film 3 covering the whole surface of an integrated circuit element 1, an aperture part 4 is opened, through which a bonding pad part 6 is arranged, so as to be connected with the metal wiring 2 of the integrated circuit element 1. Further, in a protecting film 5 covering the element protecting film 3, an aperture is formed by the bonding pad part 6, and a bonding wire 7 is bonded and connected with said aperture. In this manner, the bonding pad part 6 is newly and largely arranged, so that, even if the pad part 6 surrounded by a dotted line is corroded by the permeation of external water content, the connection between the lower metal wiring 2 and the bonding wire 7 can be maintained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特にボンイング・
パッド部の構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuit devices, and particularly to bonding and
Regarding the structure of the pad section.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路装置は、回路素子の金属配線上に
直接ボンディング・パッド部を形成するのが通常である
。Conventionally, in semiconductor integrated circuit devices, bonding pad portions are usually formed directly on metal wiring of circuit elements.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このように、従来の半導体集積回路装置は金属配線上に
直接ボンディング・パッド部が設けられるので、素子保
護膜の開口部とボンディング線の金属ボールとの間に生
じたすき間から外部からの水分の侵入がおこり、ボンデ
ィング・パッド部と金属配線との間を断線せしめること
がある。すなわち、集積回路装置の信頼性に重大な障害
を起こすのでその対策が望まれている。In this way, in conventional semiconductor integrated circuit devices, the bonding pad portion is provided directly on the metal wiring, so moisture can be absorbed from the outside through the gap created between the opening of the element protection film and the metal ball of the bonding line. Intrusion may occur and cause a disconnection between the bonding pad portion and the metal wiring. That is, since this causes a serious problem in the reliability of the integrated circuit device, countermeasures are desired.

本発明の目的は、上記の問題点に鑑み、外部からの水分
侵入によって金属配線と断線事故を生じることなきボン
ディング・パッド部を有する半導体集積回路装置を提供
することである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor integrated circuit device having a bonding pad portion that does not cause disconnection with metal wiring due to moisture intrusion from the outside.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、半導体集積回路装置は、半導体基板と
、前記半導体基板上に形成される集積回路素子と、前記
集積回路素子の全面を被覆する素子保護膜の開口部を介
し金属配線と接続するボンディング・パッド部とを備え
ることを含んで構成される。According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, an integrated circuit element formed on the semiconductor substrate, and a metal wiring connected through an opening in an element protection film covering the entire surface of the integrated circuit element. and a bonding pad section.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す半導体集積回路装置の
ボンディング・バット部近傍の断面図である。本実施例
から明らかなように、本発明によれば、集積回路素子１
の全面を被覆する素子保護膜３の金属配Ｍ２上に開口部
４を明け、この開口部４を通じて集積回路素子１の金属
配線２と接続するようにボンディング・パッド部６を設
けた後、さらに素子保護膜３上を被覆する保護膜５をこ
のボンディング・パッド部６上で開口し、この開口部に
対しボンディング・ワイヤ７をボンディング接続したも
のである。FIG. 1 is a sectional view of the vicinity of a bonding butt portion of a semiconductor integrated circuit device showing an embodiment of the present invention. As is clear from this embodiment, according to the present invention, the integrated circuit element 1
An opening 4 is formed on the metal wiring M2 of the element protection film 3 covering the entire surface of the element, and a bonding pad part 6 is provided so as to be connected to the metal wiring 2 of the integrated circuit element 1 through this opening 4. A protective film 5 covering the element protective film 3 is opened above the bonding pad portion 6, and a bonding wire 7 is bonded to this opening.

このように、ホンディング　パッド部６が新たに大きく
設けられるので、外部からの水分の侵入によりパッド部
６が点線で囲んだ部分で腐食しなとしても、下部の金属
配線２とボンディングワイヤ７との接続は保持される。In this way, since the bonding pad section 6 is newly provided with a larger size, even if the pad section 6 is not corroded in the area surrounded by the dotted line due to the intrusion of moisture from the outside, the lower metal wiring 2 and bonding wire 7 can be easily connected to each other. connection is maintained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、ボンデインク・
パッド部と集積回路素子とを保護膜をはさんで上下に接
続する構造がとられている為、外部からの水分の侵入に
よりボンディング・パッド部の周辺が腐食しても、集積
回路素子との接続に影響はなく、断線状態になることは
ない。従つ、て、半導体集積回路装置の信頼性を著しく
高め得る効果を存する。また、ボンディング・パッド部
を集積回路素子と同一平面上ではなく、その上部に配置
することができるので、チップ・サイズの縮小にも効果
をあげることができる。As explained above, according to the present invention, bonde ink and
Since the pad section and the integrated circuit element are connected vertically with a protective film in between, even if the periphery of the bonding pad section corrodes due to moisture intrusion from the outside, the connection between the integrated circuit element and the integrated circuit element remains intact. There is no effect on the connection and there is no disconnection. Therefore, there is an effect that the reliability of the semiconductor integrated circuit device can be significantly improved. Furthermore, since the bonding pad portion can be placed on top of the integrated circuit element rather than on the same plane, it is also possible to reduce the chip size.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す半導体集積回路装置の
ホンディング・パッド部近傍の断面図である。 １・・・！Ａ積回路累子、２・・・金属配線、３・・・
素子保護膜、４・・・開口部、５・・・保護膜、６・・
・ボンディング・パッド部、７・・・ボンディング・ワ
イヤ。FIG. 1 is a cross-sectional view of the vicinity of a bonding pad portion of a semiconductor integrated circuit device showing one embodiment of the present invention. 1...! A product circuit cue, 2...metal wiring, 3...
Element protective film, 4... Opening, 5... Protective film, 6...
- Bonding pad section, 7... bonding wire.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板と、前記半導体基板上に形成される集積回路
素子と、前記集積回路素子の全面を被覆する素子保護膜
の開口部を介し金属配線と接続するボンディング・パッ
ド部とを備えることを特徴とする半導体集積回路装置。A semiconductor substrate, an integrated circuit element formed on the semiconductor substrate, and a bonding pad portion connected to metal wiring through an opening in an element protection film covering the entire surface of the integrated circuit element. Semiconductor integrated circuit device.
JP63152811A 1988-06-20 1988-06-20 Semiconductor integrated circuit device Pending JPH023943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63152811A JPH023943A (en) 1988-06-20 1988-06-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63152811A JPH023943A (en) 1988-06-20 1988-06-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH023943A true JPH023943A (en) 1990-01-09

Family

ID=15548670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63152811A Pending JPH023943A (en) 1988-06-20 1988-06-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH023943A (en)

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