JPH0237735A - Mounting structure of semiconductor chip - Google Patents
Mounting structure of semiconductor chipInfo
- Publication number
- JPH0237735A JPH0237735A JP63189316A JP18931688A JPH0237735A JP H0237735 A JPH0237735 A JP H0237735A JP 63189316 A JP63189316 A JP 63189316A JP 18931688 A JP18931688 A JP 18931688A JP H0237735 A JPH0237735 A JP H0237735A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electrical wiring
- substrate
- board
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000009429 electrical wiring Methods 0.000 claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 238000007639 printing Methods 0.000 claims abstract description 7
- 229910052802 copper Inorganic materials 0.000 claims abstract description 5
- 239000010949 copper Substances 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000003822 epoxy resin Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000000704 physical effect Effects 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 229910052799 carbon Inorganic materials 0.000 abstract description 2
- 229910052738 indium Inorganic materials 0.000 abstract description 2
- 229910052742 iron Inorganic materials 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 229910052718 tin Inorganic materials 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
- 239000007787 solid Substances 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229910052750 molybdenum Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229910052715 tantalum Inorganic materials 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 5
- 238000013508 migration Methods 0.000 description 5
- 230000005012 migration Effects 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011368 organic material Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
この発明は、低コスト化、軽量化を図るために、サーマ
ルヘッド用発熱基板、イメージセンサ−用受光素子基板
、液晶表示基板上に直接半導体チップを搭載し、該素子
を駆動させる半導体装置を実装する方法を提案するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention This invention is directed to the production of semiconductor chips directly on heat generating substrates for thermal heads, light receiving element substrates for image sensors, and liquid crystal display substrates in order to reduce cost and weight. This paper proposes a method for mounting a semiconductor device that mounts a semiconductor device and drives the device.
「従来の技術Ｊ
従来の液晶表示素子等の駆動回路はガラスエポキシ基板
上に銅箔を形成した回路を設け、パッケージＩＣをハン
ダ付けすることにより作られ、それをＦＰＣにより表示
基板上の電極と１本１本結んでいた。"Conventional Technology J Conventional drive circuits for liquid crystal display elements, etc. are made by providing a circuit made of copper foil on a glass epoxy substrate, soldering a package IC, and connecting it to electrodes on the display substrate using FPC. They were tied one by one.
又、そのガラスエポキシ基板を省く為にチップ■ＣをＴ
ＡＢ法と呼ばれるポリイミド系の樹脂フィルムをベース
とするフレキシブルな基板上の配線に接続し、フィルム
端部に設けられた電極端子を表示基板上の電極に接続す
る方法、又フリップチップ法と呼ばれるＩＣのパッドに
ハンダのバンプを設け、かつ対抗する電極にハンダメツ
キを設けてバンダーハンダ接続を行う方法等がある。Also, in order to omit the glass epoxy board, chip ■C is replaced with T.
A method called the AB method, in which a polyimide resin film is connected to wiring on a flexible substrate, and an electrode terminal provided at the edge of the film is connected to an electrode on a display substrate, and an IC method, called the flip chip method. There is a method of making a bander solder connection by providing a solder bump on the pad and providing a solder plating on the opposing electrode.
表示装置の他に、回路用基板をさらに設けることは、軽
量化及び低コスト化には妨げとなっている。又ＴＡＢ法
は軽量化を目的とした方法であるが、使用するテープを
形成するのにコストがかかりすぎることが問題となって
いる。Providing a circuit board in addition to the display device is an obstacle to reducing weight and cost. Furthermore, although the TAB method is a method aimed at reducing weight, there is a problem in that it costs too much to form the tape used.
又、フリップチップ法に用いるハンダバンプの形成は隣
接するバンプ同志のショートを回避する為にＩＣ基板上
に形成する電極の集積度を上げられないことが問題点で
ある。Another problem with the formation of solder bumps used in the flip-chip method is that it is not possible to increase the degree of integration of electrodes formed on an IC substrate in order to avoid short circuits between adjacent bumps.
又、光硬化型樹脂を用いて基板と半導体チップをフェイ
スダウンで電気的に接触させる方法も考案されているが
、樹脂の熱膨張が比較的大きく、室温（２５℃程度）で
実装のプロセスを進めた場合、接合部分の信頼性は、高
温時に悪くなる結果も得られている。A method of electrically contacting the board and semiconductor chip face-down using photocurable resin has also been devised, but the thermal expansion of the resin is relatively large, making it difficult to carry out the mounting process at room temperature (approximately 25°C). If the method is advanced, the reliability of the bonded portion deteriorates at high temperatures.
ガラス基板等に直接導電性ペーストを印刷法により電気
配線を形成した場合、基板と導電性ペースト間で熱膨張
係数が１桁異なるため熱衝撃が加わった際断線が生じて
しまっている。When electrical wiring is formed by printing a conductive paste directly on a glass substrate or the like, the thermal expansion coefficient differs by one order of magnitude between the substrate and the conductive paste, resulting in disconnection when thermal shock is applied.
又、ガラス基板上の有機物をバインダーとしたものから
なる導体配線は細部配線間で基板表面上を伝わってマイ
グレーションが発生し易く、長期的な信頼性が得られな
い。Furthermore, conductor wiring made of an organic material as a binder on a glass substrate is likely to undergo migration over the surface of the substrate between small wiring lines, making it difficult to obtain long-term reliability.
「発明の構成ｊ
かかる問題を解決するため、本発明は表面に絶縁性を有
し、かつ少なくとも３２０ｎｍ〜４００ｎｍの波長を持
つ光を透過し得る基板上に該基板の持つ熱膨張係数と電
気配線の持つ熱膨張係数の間の物性を持った膜を２〜５
０μｍ厚程度形成する。その後に、Ｆｅ、Ｃｕ、Ａｇ＋
Ｐｄ−Ａｇ、Ｐｔ、ＡＩ＋Ｃ，Ｓｎ＋ Ｉｎ、Ｎｉ、Ｔ
ａ、Ｔｉ、ＳｂＭｏの内の少なくとも１種類以上の導電
性金属粒子を含んだペーストにより印刷法にて電気配線
を形成し、該配線の上部と半導体チップ上の少なくとも
表面は金、銅又ははんだからなるバンプとを機械的な接
触によって電気接触を得るため、該基板と半導体チップ
を紫外線硬化型のエポキシ樹脂で接着をする。``Structure of the Invention j'' In order to solve this problem, the present invention provides a substrate that has an insulating property on the surface and can transmit light having a wavelength of at least 320 nm to 400 nm, and the thermal expansion coefficient of the substrate and electrical wiring. A film with physical properties between the thermal expansion coefficient of 2 to 5
It is formed to a thickness of approximately 0 μm. After that, Fe, Cu, Ag+
Pd-Ag, Pt, AI+C, Sn+ In, Ni, T
Electric wiring is formed by a printing method using a paste containing conductive metal particles of at least one of a, Ti, and SbMo, and the upper part of the wiring and at least the surface of the semiconductor chip are made of gold, copper, or solder. In order to obtain electrical contact through mechanical contact with the bumps, the substrate and the semiconductor chip are bonded using an ultraviolet curing epoxy resin.
ここで、基板として使用する材料の熱膨張係数はＩ Ｘ
１０−６〜９ Ｘ １０−ｂｄ ｅ ｇ−’程度であ
りまた、電気配線材料の熱膨張係数はｌＸｌ０−’ｄｅ
ｇ −１であり、この両者のあいだに１０−’ｄｅｇオ
ーダーの緩衝層を介挿し本発明構成とする。Here, the thermal expansion coefficient of the material used as the substrate is I
The coefficient of thermal expansion of the electrical wiring material is approximately 10-6 to 9 x 10-bd e g-'
g -1, and a buffer layer on the order of 10-'deg is inserted between the two to provide the structure of the present invention.
この緩衝層としては、フェノール樹脂、アクリル樹脂等
の有機物またはこれら有機物とＳｉＯ□等の無機物の複
合体を用いることが可能である。As this buffer layer, it is possible to use an organic material such as a phenol resin or an acrylic resin, or a composite of these organic materials and an inorganic material such as SiO□.
以下、実施例により本発明を説明する。The present invention will be explained below with reference to Examples.
「実施例」 第１図に本発明の断面構造図を示す。"Example" FIG. 1 shows a cross-sectional structural diagram of the present invention.
第２図に緩衝層がある場合と無い場合のマイグレーショ
ンの発生確率を示す。Figure 2 shows the probability of migration occurring with and without a buffer layer.
第３図に緩衝層がある場合と無い場合の断線の発生確率
を示す。Figure 3 shows the probability of wire breakage occurring with and without a buffer layer.
１．１ｍｍ厚で、３６５ｎｍの波長を透過するガラス基
板（１）本実施例ではコーニング＃７０５９を用いた）
上に印刷法によってエポキシ−フェノール樹脂（２）を
３０μＩＩＩＫで印刷したのち、１５０°ＣでＮ２中で
３０分間焼成をした。その上にＡｇからな多粒子を含ん
だエポキシ樹脂ペーストを用いたスクリーン法により２
５μ曙程度の厚さの印刷を行った後、１５０°ＣＮｚ３
０分の焼成により電気配線（３）を設けた。Glass substrate with a thickness of 1.1 mm and transmitting a wavelength of 365 nm (1) Corning #7059 was used in this example)
After printing an epoxy-phenol resin (2) with 30μIIIK on it by a printing method, it was baked at 150°C in N2 for 30 minutes. On top of that, 2
After printing with a thickness of about 5μ, 150°CNz3
Electric wiring (3) was provided by firing for 0 minutes.
３６５ｎｍに光の吸収を持つ光硬化型エポキシ樹脂（６
）を、その出力端にメツキ法で設けた金よりなるバンプ
（４）を有する半導体チップ（５）上にディスペンスし
、該配線との位置合わせを行った後に、１２〜１３．５
Ｋｇ／ｃｍ” の荷重をかけて、基板と半導体チップ
を発着させた。Photocurable epoxy resin that absorbs light at 365 nm (6
) is dispensed onto the semiconductor chip (5) having bumps (4) made of gold provided by the plating method on the output end, and after alignment with the wiring, 12 to 13.5
A load of 1 kg/cm'' was applied to the substrate and the semiconductor chip.
その後に、３６５ｎ−に発光ピークを有する高圧水銀ラ
ンプにより２０００ｍＪ／ｃｍ２ のエネルギーを基
板側より照射しＩＣチップを実装した。Thereafter, an IC chip was mounted by irradiating energy of 2000 mJ/cm2 from the substrate side using a high-pressure mercury lamp having an emission peak at 365 n-.
従来技術の場合、本発明の緩衝層がなく基板上に直接電
気配線が形成され、その電気配線上に紫外線硬化樹脂が
おおって設けられている。この時配線間の基板と紫外線
硬化樹脂との間に水分が存在し、この水分のため配線間
のマイグレーションが発生する。In the case of the prior art, the buffer layer of the present invention is not provided, and electrical wiring is formed directly on the substrate, and the electrical wiring is covered with an ultraviolet curing resin. At this time, moisture exists between the substrate and the ultraviolet curing resin between the wirings, and this moisture causes migration between the wirings.
一方本発明の場合電気配線は直接基板上に形成されず緩
衝層上に形成される。しかもこの緩衝層は加熱処理をし
て形成されるため紫外線硬化樹脂との間に水分は存在し
ない。よって配線間のマイグレーションの発生が少なく
なる。On the other hand, in the case of the present invention, the electrical wiring is not formed directly on the substrate but on the buffer layer. Moreover, since this buffer layer is formed by heat treatment, no moisture exists between it and the ultraviolet curing resin. Therefore, the occurrence of migration between wirings is reduced.
第２図に本発明構造と従来例とのマイグレーションの発
生率を示す。明らかに本発明構造のほうが発生率が低い
ことがわかる。同様に配線の断線発止率の結果を第３図
に示す。FIG. 2 shows the incidence of migration between the structure of the present invention and the conventional example. It is clearly seen that the structure of the present invention has a lower occurrence rate. Similarly, the results of the occurrence rate of wire breakage are shown in FIG.
第２図及び第３図ともΔ印のプロットが従来の構造の場
合であり○印のプロットが本発明構造の場合である。な
お、この依頼性試験には１０００個のサンプルを対象と
して行った。In both FIGS. 2 and 3, the plots marked Δ are for the conventional structure, and the plots marked ○ are for the structure of the present invention. Note that this dependability test was conducted on 1000 samples.
本発明構成により熱歪による断線に対する信頼性を向上
させることができた。With the configuration of the present invention, reliability against disconnection due to thermal strain could be improved.
またそのために特に製造コストを上昇させることもなく
、信頼性を改善することができた。Furthermore, reliability could be improved without particularly increasing manufacturing costs.
第１図は本発明の断面構造を示す。
第２図及び第３図は本発明構造の信頼性のデータを示す
。FIG. 1 shows a cross-sectional structure of the present invention. 2 and 3 show reliability data for the structure of the present invention.
Claims (1)
長の光を少なくとも透過する基板上に、少なくとも１種
類以上の導電性粒子を含んだ導電性ペーストを印刷法に
より電気配線を形成する方法において、該基板と電気配
線の間に熱膨張係数が基板のもつ物性値より大きく、電
気配線を構成する材料の物性値より小さい物質を有する
事を特徴とする半導体チップの実装構造。 ２、特許請求の範囲第１項において電気配線と、半導体
チップ上のバンプとを機械的な接触によって電気接触を
させるため、該基板と半導体チップをＵＶ硬化型のエポ
キシ樹脂で接着して基板と半導体チップを密着させるこ
とを特徴とする半導体チップの実装構造。 ３、特許請求の範囲第１項において、該電気配線と半導
体チップ上の半田バンプとを合金的に電気接触させるこ
とを特徴とする半導体チップの実装構造。 ４、特許請求の範囲第２項において、前記バンプの少な
くとも表面は金、銅又ははんだより選ばれたことを特徴
とする半導体チップの実装構造。[Claims] 1. A conductive paste containing at least one type of conductive particles is applied by a printing method onto a substrate that has an insulating surface and transmits at least light with a wavelength of 320 to 400 nm. A method for forming an electrical wiring, comprising a substance having a coefficient of thermal expansion larger than the physical property value of the substrate and smaller than the physical property value of the material constituting the electrical wiring between the substrate and the electrical wiring. Implementation structure. 2. In claim 1, in order to make electrical contact between the electrical wiring and the bumps on the semiconductor chip through mechanical contact, the substrate and the semiconductor chip are bonded together using a UV-curable epoxy resin. A semiconductor chip mounting structure characterized by closely adhering semiconductor chips. 3. A semiconductor chip mounting structure according to claim 1, characterized in that the electrical wiring and the solder bumps on the semiconductor chip are electrically contacted in an alloy manner. 4. The semiconductor chip mounting structure according to claim 2, wherein at least the surface of the bump is selected from gold, copper, or solder.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63189316A JPH0237735A (en) | 1988-07-27 | 1988-07-27 | Mounting structure of semiconductor chip |
| US07/855,481 US5194934A (en) | 1988-07-27 | 1992-03-23 | Mounting structure for a semiconductor chip having a buffer layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63189316A JPH0237735A (en) | 1988-07-27 | 1988-07-27 | Mounting structure of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0237735A true JPH0237735A (en) | 1990-02-07 |
Family
ID=16239320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63189316A Pending JPH0237735A (en) | 1988-07-27 | 1988-07-27 | Mounting structure of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0237735A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006154726A (en) * | 2004-11-26 | 2006-06-15 | Gunko Kagi (Shenzhen) Yugenkoshi | Flexible circuit board and liquid crystal display device using same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51150671A (en) * | 1975-06-19 | 1976-12-24 | Sharp Kk | Method of fixing electronic parts |
| JPS5512749A (en) * | 1978-07-12 | 1980-01-29 | Mitsubishi Electric Corp | Compound integrated circuit |
| JPS57163919A (en) * | 1981-03-20 | 1982-10-08 | Philips Nv | Method of forming protruded contact |
| JPS61287238A (en) * | 1985-06-14 | 1986-12-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6354737A (en) * | 1986-08-25 | 1988-03-09 | Nec Corp | Method of packaging integrated circuit chip |
-
1988
- 1988-07-27 JP JP63189316A patent/JPH0237735A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51150671A (en) * | 1975-06-19 | 1976-12-24 | Sharp Kk | Method of fixing electronic parts |
| JPS5512749A (en) * | 1978-07-12 | 1980-01-29 | Mitsubishi Electric Corp | Compound integrated circuit |
| JPS57163919A (en) * | 1981-03-20 | 1982-10-08 | Philips Nv | Method of forming protruded contact |
| JPS61287238A (en) * | 1985-06-14 | 1986-12-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6354737A (en) * | 1986-08-25 | 1988-03-09 | Nec Corp | Method of packaging integrated circuit chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006154726A (en) * | 2004-11-26 | 2006-06-15 | Gunko Kagi (Shenzhen) Yugenkoshi | Flexible circuit board and liquid crystal display device using same |
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