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Fujitsu Ltd
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Fujitsu Ltd
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Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP8917981ApriorityCriticalpatent/JPS57204628A/ja
Publication of JPS57204628ApublicationCriticalpatent/JPS57204628A/ja
Publication of JPH0237728B2publicationCriticalpatent/JPH0237728B2/ja
Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs