JPH0236410A - Acceleration/deceleration device - Google Patents

Abstract

PURPOSE:To prevent circuit constitution and a program from becoming complicated by sequentially connecting specified shift register blocks to an operation part in serial and connecting a division means to a shift register block in a final level. CONSTITUTION:The operation part 1, shift register blocks B1-Bm in an (m) level, which are sequentially connected in serial with the operation part 1 and the divider 4 connected with the block Bm in the final level are provided. 2<i-1> number of shift registers and one addition element 3 for adding the output of 2<i-1>-numbered shift register and the input of the block Bi are included in a shift register block Bi in an (i)-numbered level. The divider 4 divides the addition result of the addition element 3 in the block Bi in the final level by a prescribed constant 2<m> and outputs it. Since addition operation is executed by the number of times equivalent to the number of the levels of the shift register block, the number of times of additional operation does not increase so much even if the number of the shift registers increases, and circuit constitution and the program is prevented from becoming complicated.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is useful for accelerating or decelerating a movable part in order to move the movable part to a target point in, for example, an industrial robot or a machine tool. Depends on the acceleration/deceleration device used.

<Prior art> As shown in FIG. 7, a conventional acceleration/deceleration device of this type includes a calculation unit 11 that calculates and outputs the amount of movement at each sampling period.
, shift registers 12a to 12n that store the movement amount for a plurality of samplings, and a multiplier 13 that multiplies the data stored in each shift register by a preset coefficient.
a to 13n, an adder 14 that adds the multiplication results of each multiplier, and a divider 15 that divides the addition result of the adder 14 by the sum of the coefficients has been proposed ( JP-A-59-90107).

When data regarding the amount of movement, command speed, etc. is given to this type of acceleration/deceleration device, the output of the calculation unit 11 is
In the figure, the configuration is as shown by a solid line A, and as a result, a trapezoidal acceleration/deceleration characteristic as shown by a broken line B is obtained as an output of this acceleration/deceleration device.

This acceleration/deceleration characteristic is composed of an acceleration portion 9, a constant velocity portion, and a deceleration portion. , it is also possible to form a curved shape as shown by chain lines C1 and Cz in the figure. In the case of the figure, the coefficient multiplied by each of the multipliers 13a to 13n is set to 1, and the acceleration/deceleration characteristic at this time is a straight line in the acceleration portion and the deceleration portion.

FIG. 8 shows an example of the main parts of the acceleration/deceleration device when the coefficient is set to 1, and includes three shift registers 12.
a-=12c, an adder 14 made up of three addition elements 14a to 14c, and one divider 15.

Now, if the pulse transfer function of each shift register 12a to 12c is represented by z -1 and the input of the shift register 12a is represented by u(t), then the adder 14 performs addition three times in total by each addition element 14a to 14c, Calculate the next output y.

y= (1+z-'+z-''+z-')u(t) <Problem to be solved by the invention> In the case of the above device example, three addition operations corresponding to the number of shift registers are executed. However, as the number of shift registers increases, the number of additions increases proportionally, so
This has the disadvantage that the circuit configuration and program become complicated, resulting in high cost and reliability.

This invention was made in view of the above problem, and aims to provide a new acceleration/deceleration device that has a simplified circuit configuration and program by devising the configuration of the circuit including the shift register. do.

<Means for solving the problem> In order to achieve the above object, the acceleration/deceleration device of the present invention has the following features:
M stages (where m is an integer of 1 or more) of shift register blocks are sequentially connected in series to the calculation means that calculates and outputs the amount of movement at each sampling period, and the final stage shift register block is connected to the calculation means that calculates and outputs the movement amount. A dividing means for dividing by a predetermined value is connected.

In the present invention, the first stage of the m-stage shift register block (where i is an integer and 1≦i≦m
) for storing the input of the shift register block for 21-1 samplings shifted every sampling period, and a shift register for adding the output of this shift register and the input of the shift register block. It consists of an adding means.

Effect> In the device of the present invention, the addition operation is executed the number of times corresponding to the number of stages of the shift register block, so even if the number of shift registers increases, the number of addition operations is not so large. This prevents the circuit configuration and program from becoming complicated.

<Embodiment> FIG. 1 shows an example of the circuit configuration of an acceleration/deceleration device according to an embodiment of the present invention.

The illustrated acceleration/deceleration device is for, for example, when moving the hand portion of an industrial robot to a target point, after accelerating it, it shifts to a uniform motion, and then decelerates and stops at the target point, It is connected to an arithmetic unit 1, shift register blocks B, ~B, of m stages (where m is an integer of 1 or more) sequentially connected in series to this arithmetic unit 1, and a final stage shift register block B. and a divider 4.

When the calculation unit 1 is given data regarding the amount of movement, commanded speed, etc., it calculates the amount of movement at each sampling period.
A calculation output as shown in FIG. 3(1) is given to the first stage shift register block B.

Among the m-stage shift register blocks B, ~B,
The first stage (where i is an integer and 1≦i≦m) shift register block Bi has 2i-1 shift registers, and the output of the 21-1st shift register and its shift register block B. It includes one addition element for adding human power and one addition element.

FIG. 2 (1) shows the configuration of the first stage shift register block B, which includes one shift register 2a, the output of the shift register 2a, and the shift register block B.
It includes one addition element 3 for adding the inputs.

FIG. 2 (2) shows the second stage shift register block B2.
shows the configuration of two shift registers 2a and 2b, and one addition element 3 for adding the output of the rear shift register 2b and the input of this shift register block B2.
Contains.

Figure 2 (3) shows the third stage shift register block B3.
shows the configuration of four shift registers 2a, 2b, 2c.
, 2d, and 1 for adding the output of the last shift register 2d and the input of this shift register block B3.
It includes 3 addition elements.

FIG. 2 (4) shows the m-th shift register block B1.
shows the configuration of m shift registers 2a, 2b, 2C.
, -..., 2n, and one addition element 3 for adding the output of the last shift register 2n and the input of this shift register block B.

Each of these shift register blocks 81-B.

For example, the first stage shift register block Bi
Each shift register 2a+2b constitutes.

. . . corresponds to 2"-1 samplings obtained by sequentially shifting the input to the shift register block Bi at each sampling period. It is for storing data, and corresponds to 21-1 samplings. The output of the second shift register and the input of the shift register block B! are added by an addition element 3, and the addition result is given to a divider 4.

This divider 4 is for dividing the addition result by the addition element 3 by a predetermined constant (2i'' in this case), thereby producing a trapezoidal calculation output as shown in FIG. 3 (2). is obtained.

Note that the computation output of the computation unit 1 has a complicated form as shown in FIG. 4 (1) in the first stage shift register block B.
1, the arithmetic output of the divider 4 also takes a correspondingly complicated form as shown in FIG. 4(2).

FIG. 5 shows, as a specific example, a two-stage (m=2) shift register block B0. This shows an acceleration/deceleration device composed of Bz.

One shift register 2a forming the first stage shift register block B1 and two shift registers 2a forming the second stage shift register block B2.
, 2b is represented by 2- +, and the input of the first stage shift register block B is represented by u(t), then the output y of the second stage shift register block B2 is as follows, and the above-mentioned 8th This corresponds to the conventional example shown in the figure.

y= (1+z-')(1+z-")u(t)= (1
+z-'+z-''+z-')u(t) Comparing the conventional example shown in FIG. 8 with the one of the present invention shown in FIG. 5, the number of additions in the former is three, while , the latter is twice, and the latter has a smaller number of additions.

Similarly, a three-stage (m=3) shift register block B1
．． In the case of the acceleration/deceleration device composed of Bz and B3, the number of additions is three times, but in the conventional example corresponding to this, the number of additions is seven times, and the number of additions in the present invention is significantly higher. It becomes less.

Similarly, m-stage shift register block B+.

B! + Bff+ . . . In the case of an acceleration/deceleration device composed of B1, the number of additions is m times, whereas in the conventional example corresponding to this, the number of additions is (2 @ 1) times. , the difference between the two becomes more significant as the number of shift registers increases.

In addition, in FIG. 5, the second stage shift register block B! It is also possible to replace the two shift registers 2a and 2b constituting the shift register 2 with a shift register 2 whose pulse transfer function is represented by z-2 and which shifts once every two sampling periods, as shown in FIG. be.

<Effects of the Invention> As described above, the present invention sequentially connects shift register blocks having a predetermined number of shift registers and one addition means to the calculation unit in series, and connects the shift register blocks to the final stage shift register block. Since a dividing means for dividing the output by a predetermined value is connected, it is possible to construct an acceleration/deceleration device that requires fewer additions compared to conventional examples, and it minimizes the complexity of the circuit configuration and program, reducing costs and reliability. It achieves the remarkable effects of achieving the purpose of the invention, such as preventing the deterioration of cetacean quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an acceleration/deceleration device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of shift register blocks in each stage, and FIG. 3 is a block diagram showing the configuration of the shift register block in each stage. FIG. 4 is an explanatory diagram showing other examples of the calculation outputs of the calculation unit and the divider. FIG. 5 is a block diagram showing a specific example of the shift register block.
9 is a block diagram showing another example of FIG. 5, FIGS. 7 and 8 are block diagrams showing the configuration of a conventional acceleration/deceleration device, and FIG.
The figure is an explanatory diagram showing the calculation outputs of the calculation unit and the divider. 1... Arithmetic unit 81-BII... Shift register block 2a-2
n...Shift register 4...Divider

Claims (1)

[Claims] M stages (where m is an integer of 1 or more) of shift register blocks are sequentially connected in series to a calculation means that calculates and outputs the amount of movement in each sampling period, and a final stage of shift register blocks is connected in series. A division means for dividing the output by a predetermined value is connected to the shift register block, and among the m-stage shift register blocks, the i-th shift register block (i is an integer and 1≦i≦m) The register block is a shift register for storing 2^i^-^1 samplings whose input is shifted every sampling period, and a shift register for adding the output of this shift register and the input of the shift register block. An acceleration/deceleration device comprising an addition means.