JPH0236012B2 - - Google Patents

Info

Publication number
JPH0236012B2
JPH0236012B2 JP59272451A JP27245184A JPH0236012B2 JP H0236012 B2 JPH0236012 B2 JP H0236012B2 JP 59272451 A JP59272451 A JP 59272451A JP 27245184 A JP27245184 A JP 27245184A JP H0236012 B2 JPH0236012 B2 JP H0236012B2
Authority
JP
Japan
Prior art keywords
storage
key
segment
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59272451A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61165156A (ja
Inventor
Kunio Nakabayashi
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59272451A priority Critical patent/JPS61165156A/ja
Publication of JPS61165156A publication Critical patent/JPS61165156A/ja
Publication of JPH0236012B2 publication Critical patent/JPH0236012B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59272451A 1984-12-24 1984-12-24 記憶キ−制御方式 Granted JPS61165156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59272451A JPS61165156A (ja) 1984-12-24 1984-12-24 記憶キ−制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59272451A JPS61165156A (ja) 1984-12-24 1984-12-24 記憶キ−制御方式

Publications (2)

Publication Number Publication Date
JPS61165156A JPS61165156A (ja) 1986-07-25
JPH0236012B2 true JPH0236012B2 (sv) 1990-08-15

Family

ID=17514101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59272451A Granted JPS61165156A (ja) 1984-12-24 1984-12-24 記憶キ−制御方式

Country Status (1)

Country Link
JP (1) JPS61165156A (sv)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583175A (ja) * 1981-06-30 1983-01-08 Fujitsu Ltd 仮想記憶制御装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583175A (ja) * 1981-06-30 1983-01-08 Fujitsu Ltd 仮想記憶制御装置

Also Published As

Publication number Publication date
JPS61165156A (ja) 1986-07-25

Similar Documents

Publication Publication Date Title
US5530829A (en) Track and record mode caching scheme for a storage system employing a scatter index table with pointer and a track directory
US4386402A (en) Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
JPS6376034A (ja) 多重アドレス空間制御方式
US4318175A (en) Addressing means for random access memory system
JPH04308953A (ja) 仮想アドレス計算機装置
EP0323123B1 (en) A storage control system in a computer system
JPH05197619A (ja) マルチｃｐｕ用メモリ制御回路
JPS5844263B2 (ja) 記憶制御回路
US4493030A (en) Plural data processor groups controlling a telecommunications exchange
JPH0540694A (ja) キヤツシユメモリ装置
JPH0236012B2 (sv)
EP0787326B1 (en) System and method for processing of memory data and communication system comprising such system
GB2221066A (en) Address translation for I/O controller
KR920003845B1 (ko) 개인용 컴퓨터의 사용자를 위한 rom의 영역 확장 시스템
JPS5953588B2 (ja) メモリ・インタリ−ブ制御方式
JPH037980B2 (sv)
GB2099619A (en) Data processing arrangements
KR900009212Y1 (ko) 어드레스 제어장치
JPS6136669B2 (sv)
JPH0241772B2 (sv)
JPH01140342A (ja) 仮想計算機システム
JPH04182753A (ja) キャッシュメモリ
JPS6174040A (ja) アドレス拡張方法
JPH04205535A (ja) コピーオンライト方式
JPH0244445A (ja) データ処理装置