JPH0234988A - Printed board and manufacture thereof - Google Patents

Printed board and manufacture thereof

Info

Publication number
JPH0234988A
JPH0234988A JP18521888A JP18521888A JPH0234988A JP H0234988 A JPH0234988 A JP H0234988A JP 18521888 A JP18521888 A JP 18521888A JP 18521888 A JP18521888 A JP 18521888A JP H0234988 A JPH0234988 A JP H0234988A
Authority
JP
Japan
Prior art keywords
hole
solder
holes
conductor
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18521888A
Other languages
Japanese (ja)
Inventor
Kazuo Chiba
千葉 和雄
Shozo Sakayori
酒寄 祥三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP18521888A priority Critical patent/JPH0234988A/en
Publication of JPH0234988A publication Critical patent/JPH0234988A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To suppress flow-down of solder into a through hole by forming a solder land partly on a whole periphery on the upper face of the hole, and soldering a conductor thereon. CONSTITUTION:A solder land 37 formed on a conductive foil 11 on the periphery of the upper face of a through hole 13 is formed merely on the part of a side extended at the intermediate 24 of a conductive conductor 21. Thus, a resist film 15 formed on the foil 11 is formed on other surface except the land 37, and a resist film 15 is formed on the part of the side opposite to the side extended at the intermediate 24 of the conductor 21. A solder 36 adheres to the land 37, and the foil 11 is connected to the intermediate 24 of the conductor. Thus, when the land 37 formed on the part of the whole periphery of the hole is soldered by placing the conductor thereon, the solder melted through the hole 13 or the conductor inserted into the hole is prevented from flowing out.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電気回路を形成するプリント基板の新規な構造
及びその製造方法に関する。更に詳しくはプリント基板
の表面と裏面の回路を導体を介して接続する際に使用し
て最適な構造及び製法に係る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a novel structure of a printed circuit board forming an electric circuit and a method of manufacturing the same. More specifically, it relates to an optimal structure and manufacturing method for use when connecting circuits on the front and back sides of a printed circuit board via conductors.

従来の技術 第3図は、従来のプリント基板の断面図、第4図は第3
図のA部拡大平面図を示す。第3、第4図において、1
0は絶縁性基板、11は基板10の表面に配設されたプ
リント導電箔、12は基板10の裏面に配設されたプリ
ント導電箔、13は導電箔11の一端部に基板10を通
して裏面へ穿設された透孔、14は導電箔12の一端部
に基板10を通して表面へ穿設された透孔、透孔13と
14は隣接して形成される。15は基板10と導電箔1
1の表面に設けられたレジスト校で、半田16が付着さ
れる半田ランド部17を除いた表面に設けられる。図示
例の場合、半田ランド部17は透孔13の表面の開口全
周(周囲の全部)に形成される。18は基板10と導電
箔12の表面に設けられたレジスト膜で、半田19が付
着される半田ランド部20を除いた表面に設けられる。
Conventional technology Fig. 3 is a sectional view of a conventional printed circuit board, and Fig. 4 is a cross-sectional view of a conventional printed circuit board.
An enlarged plan view of part A in the figure is shown. In Figures 3 and 4, 1
0 is an insulating board, 11 is a printed conductive foil arranged on the front surface of the board 10, 12 is a printed conductive foil arranged on the back side of the board 10, and 13 is a printed conductive foil that passes the board 10 through one end of the conductive foil 11 to the back side. A through hole 14 is formed at one end of the conductive foil 12 through the substrate 10 to the surface thereof, and the through holes 13 and 14 are formed adjacent to each other. 15 is a substrate 10 and a conductive foil 1
1, and is provided on the surface excluding the solder land portion 17 to which the solder 16 is attached. In the case of the illustrated example, the solder land portion 17 is formed around the entire opening (the entire periphery) of the surface of the through hole 13 . Reference numeral 18 denotes a resist film provided on the surfaces of the substrate 10 and the conductive foil 12, excluding the solder land portion 20 to which the solder 19 is attached.

図示例の場合、半田ランド部20は透孔14の表面の開
口全周に形成される。21は導電線で、一端部22が透
孔13に基板10の表面から裏面へ貫挿され、裏面でク
リンチされる。導電線の他端部23は透孔14に基板1
0の表面から裏面へ貫挿され、裏面でクリンチされる。
In the illustrated example, the solder land portion 20 is formed on the surface of the through hole 14 all around the opening. A conductive wire 21 has one end 22 inserted into the through hole 13 from the front surface to the back surface of the substrate 10, and is clinched on the back surface. The other end 23 of the conductive wire is inserted into the through hole 14 of the substrate 1.
It is penetrated from the front side of 0 to the back side and clinched on the back side.

導電線21の中間部24は透孔13と14の間で基板1
0の表面に延びる。半田16と19は、導電線の両端部
22と23がクリンチされた後、半田ランド部17と2
0に付着され、半田16と19を介して導電線21が導
電箔11と12に電気的に接続される。
The intermediate portion 24 of the conductive wire 21 is connected to the substrate 1 between the through holes 13 and 14.
Extends to the surface of 0. Solders 16 and 19 are applied to solder lands 17 and 2 after both ends 22 and 23 of the conductive wire are clinched.
A conductive wire 21 is electrically connected to the conductive foils 11 and 12 via the solders 16 and 19.

これによって、導電箔11と12は導電線21を介して
電気的に接続される。
Thereby, the conductive foils 11 and 12 are electrically connected via the conductive wire 21.

導電線21はプリント基板の表面と裏面に形成された導
電箔11と12を電気的に接続する機能を有する。
The conductive wire 21 has the function of electrically connecting the conductive foils 11 and 12 formed on the front and back surfaces of the printed circuit board.

従来の技術の課題 基板10の表面を上面にして半田16で半田ランド部1
7と導電線の一端部22を接続する場合、リフロー半田
付は方法で行われる。リフロー半田付は方法は、半田ラ
ンド部17の表面にクリーム半田を塗布した後、加熱炉
を通しそのクリーム半田を溶解し、その後冷却して固着
する。しかしながら、クリーム半田が溶解した際、その
溶解した半田は流動性を有するので、透孔13又は透孔
13に挿通された導電線の一端部22を通して流出し、
半田ランド部17上で一端部22との間に固着され、接
続すべき半田16の量が不足し、半田付けの信頼性が低
下するという欠点があった。
Problems with the Prior Art Solder land portion 1 is soldered with solder 16 with the surface of the board 10 facing upward.
7 and one end 22 of the conductive wire, reflow soldering is performed by the method. The reflow soldering method involves applying cream solder to the surface of the solder land portion 17, melting the cream solder through a heating furnace, and then cooling and fixing the solder. However, when the cream solder melts, since the melted solder has fluidity, it flows out through the through hole 13 or one end portion 22 of the conductive wire inserted through the through hole 13.
There is a drawback that the amount of solder 16 that is fixed on the solder land portion 17 and the one end portion 22 for connection is insufficient, and the reliability of soldering is reduced.

又基板10の表面と裏面に形成された導電箔11と12
を導電線21を用いて接続する場合、導電線21の両端
部22と23に半田16と19を介して導電箔11と1
2が接続される。この場合半田16と19は同一の透孔
13又は14の両面に形成されることを避け、第3図に
示す様に隣接した透孔13と14の一方の表面と他方の
裏面に形成される。その理由は、半田16と19が同一
の透孔、例えば第3図の13の両面に形成される場合を
考えると、第3図の導電線の一端部22は基板10の透
孔13の表面と裏面の全周が半11】16で閉塞される
。すると、透孔13内に発生するフラックス等のガスの
逃げ道が無くなり、やむなく溶解した半田16の中を通
って外部へ逃げる。
Also, conductive foils 11 and 12 formed on the front and back surfaces of the substrate 10
When connecting using conductive wire 21, conductive foils 11 and 1 are connected to both ends 22 and 23 of conductive wire 21 via solders 16 and 19.
2 are connected. In this case, solders 16 and 19 are not formed on both sides of the same through hole 13 or 14, but are formed on one surface and the other back surface of adjacent through holes 13 and 14, as shown in FIG. . The reason for this is that if solders 16 and 19 are formed on both sides of the same through hole, for example 13 in FIG. 3, one end 22 of the conductive wire in FIG. The entire circumference of the back surface is closed with half 11]16. Then, there is no way for gas such as flux generated in the through hole 13 to escape, and it has no choice but to escape to the outside through the melted solder 16.

このため、フラックスガスによる空洞が生じ、半田16
の付着が不完全となり、半田付けの信頼性が損なわれる
Therefore, a cavity is created due to the flux gas, and the solder 16
The adhesion becomes incomplete and the reliability of soldering is impaired.

そこで、第3図のように導電線の両端部22と23は隣
接した透孔13と14を用いて半田付は接続される。し
かしながら、これによると、透孔13と14が2個必要
となり、同一の透孔の両面で半【口付けできず、集積性
が低下するという欠点があった。
Therefore, as shown in FIG. 3, the ends 22 and 23 of the conductive wire are connected by soldering using the adjacent through holes 13 and 14. However, according to this method, two through holes 13 and 14 are required, and there is a drawback that semi-opening cannot be performed on both sides of the same through hole, resulting in a decrease in the integration property.

課題を解決するための手段 本発明は透孔の上面に形成される半田ランド部を透孔の
全周の一部に形成し、この半田ランド部りに導電体を延
出させるようにした。
Means for Solving the Problems In the present invention, a solder land portion formed on the upper surface of a through hole is formed on a part of the entire circumference of the through hole, and a conductor is made to extend over this solder land portion.

透孔の表面と裏面に形成される半田ランド部の少な(と
も一方を透孔の全周の一部に形成した。
The number of solder lands formed on the front and back surfaces of the through hole was small (both sides were formed on a part of the entire circumference of the through hole).

そして、この透孔の表面と裏面に形成された半田ランド
都に導電体を半田付は接続した。
Then, a conductor was soldered and connected to the solder lands formed on the front and back sides of this through hole.

作用 透孔の全周の一部に形成された半田ランド部は、その上
に導電体を載せて半田付けされると、透孔又は透孔に挿
通された導電体を通して溶解した半田が流出されること
を防止できる。
When a conductor is placed on the solder land formed on a part of the circumference of the working through hole and soldered, the molten solder flows out through the through hole or the conductor inserted through the through hole. This can be prevented.

又透孔の全周の一部に形成された半田ランド部は、その
上に半田が付着されると、半田は透孔を閉塞しない。し
たがって、フラックス等のガスの逃げ孔を形成する。
Furthermore, when solder is applied onto the solder land portion formed on a portion of the entire circumference of the through hole, the solder does not close the through hole. Therefore, an escape hole for gas such as flux is formed.

実施例 第1図は本発明の一実施例の断面図、第2図は第1図の
A部拡大平面図である。第1図、第2図において、第3
図、第4図と同一部分は同一符号を付し、説明を省略す
る。新規な点は、透孔13の上面周囲で、導電箔11の
表面に形成される半ば1ランド部37が、導電線21の
中間24の延出された側の一部にのみ形成されているこ
とである。
Embodiment FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is an enlarged plan view of section A in FIG. In Figures 1 and 2, the 3rd
The same parts as those in FIG. The novel point is that the mid-1 land portion 37 formed on the surface of the conductive foil 11 around the upper surface of the through hole 13 is formed only on a part of the extended side of the middle 24 of the conductive wire 21. That's true.

このために導電箔11の表面に形成されるレジスト膜1
5は半田ランド部37を除く他の表面に形成され、第3
図の場合と特に異なる点は、透孔13の上面周囲で、導
電線21の中間部24の延出された側と反対側の一部に
、レジスト膜15が形成されていることである。半田ラ
ンド部37は、透孔13の上面周囲の全体の略半分程度
が好ましい。半田36は半田ランド部37に付着され、
導電箔11と導電線の中間部24を接続する。
For this purpose, a resist film 1 is formed on the surface of the conductive foil 11.
5 is formed on the surface other than the solder land portion 37, and the third
A particular difference from the case shown in the figure is that a resist film 15 is formed on a part of the upper surface of the through hole 13 on the side opposite to the side where the intermediate portion 24 of the conductive wire 21 extends. The solder land portion 37 is preferably about half of the entire circumference of the upper surface of the through hole 13 . The solder 36 is attached to the solder land portion 37,
The conductive foil 11 and the intermediate portion 24 of the conductive wire are connected.

新規な点の他の1つは、透孔13の下面にもプリント導
電箔38が配設されており、透孔13の下面全周で導電
箔38の表面に半田ランド部39が形成されており、こ
の半田ランド部39に半田40が付着されていることで
ある。
Another novel point is that a printed conductive foil 38 is also provided on the lower surface of the through hole 13, and a solder land portion 39 is formed on the surface of the conductive foil 38 all around the lower surface of the through hole 13. In addition, solder 40 is attached to this solder land portion 39.

レジスト膜18は半田ランド部39と20を除いた裏面
に形成される。半田36が半田ライド部37を上面にし
た状態で設けられる場合、リフロー半)El付は方法が
使用されるのが一般的である。
The resist film 18 is formed on the back surface excluding the solder land portions 39 and 20. When the solder 36 is provided with the solder riding portion 37 facing upward, a reflow soldering method is generally used.

この場合、半田ランド部37の表面にクリーム半田が塗
布され、その後に加熱炉等に通してクリーム半田が加熱
され、溶解される。しかる後、冷却して半田36が固化
される。その際、半田36は透孔13の上面で全周の一
部にのみ形成された半田ランド部37上に付着されるた
め、溶解状態の半田36が透孔13や透孔13の中に挿
通された導電線の一端部22を通して流下することが防
止される。
In this case, cream solder is applied to the surface of the solder land portion 37, and then passed through a heating furnace or the like to heat and melt the cream solder. Thereafter, the solder 36 is solidified by cooling. At this time, since the solder 36 is attached to the solder land portion 37 formed only on a part of the entire circumference on the upper surface of the through hole 13, the solder 36 in a molten state is inserted into the through hole 13 and the through hole 13. This prevents the conductive wire from flowing down through one end 22 of the conductive wire.

また、半田ランド部37と39と20の半田36と40
と19が全てディップ(フロー)半田付は方法で形成さ
れる場合、又は表面の半田ランド部37の半田36がリ
フロー半田付は方法で形成され、裏面の半田ランド部3
9と20の半田40と19がディップ半田付は方法で形
成される場合、透孔13の上面には半田36が閉塞され
ず開口されるため、半田40が形成される場合に透孔1
3中に生じるフラックス等のガスが上方へ逃げ出すこと
ができ、半田40と36の半田付は性に悪影響を与える
ことがなく、半田付けの信頼性が損なわれることがない
In addition, the solder lands 37, 39, and 20 are solder 36 and 40.
and 19 are all formed using the dip (flow) soldering method, or the solder 36 on the solder land 37 on the front surface is formed using the reflow soldering method, and the solder land 3 on the back surface is formed using the reflow soldering method.
When the solders 40 and 19 of 9 and 20 are formed by the dip soldering method, the solder 36 is not closed on the top surface of the through hole 13 and is opened, so when the solder 40 is formed, the through hole 1
Gas such as flux generated in the solder 3 can escape upward, and the soldering properties of the solders 40 and 36 are not adversely affected, and the reliability of the soldering is not impaired.

更には透孔13の両面に半田36と40を形成すること
ができるから、透孔13の両面に導電箔11と38を形
成することができ、実装密度を向上できる。すなわち、
従来の第3図の場合は、隣接する透孔13と14の間に
導電線24を配置した場合、透孔13の一方の面と透孔
14の一方の面にしか半田16と19を設けることがで
きなかったのに対し、本発明の第1図の場合は、透孔1
3の両面と透孔14の両面に半田36と40を必要に応
じて設けることができ、基板設計上有利である。
Furthermore, since the solders 36 and 40 can be formed on both sides of the through hole 13, the conductive foils 11 and 38 can be formed on both sides of the through hole 13, and the packaging density can be improved. That is,
In the conventional case of FIG. 3, when the conductive wire 24 is placed between the adjacent through holes 13 and 14, the solders 16 and 19 are provided only on one side of the through hole 13 and one side of the through hole 14. On the other hand, in the case of FIG. 1 of the present invention, the through hole 1
Solders 36 and 40 can be provided on both sides of the substrate 3 and on both sides of the through hole 14 as necessary, which is advantageous in terms of board design.

導電4!21は基板10の両面に形成した導電箔11と
38等を電気的に接続することができ、透孔13の内面
にメツキを施こすスルーホールに比して安価に提供でき
る。
The conductor 4!21 can electrically connect the conductive foils 11 and 38 formed on both sides of the substrate 10, and can be provided at a lower cost than a through hole in which the inner surface of the through hole 13 is plated.

基板10の両面に半田36と40.19を施こす場合、
上面はリフロー法により、下面はディップ法により行う
ことができ、基板10を反転せず、基板の上面にチップ
部品やフラットパックICを半田付けし、下面にリード
線付きの部品を半田付けする場合、それらと同時に行う
ことができる。
When applying solder 36 and 40.19 to both sides of the board 10,
The top surface can be soldered by the reflow method, and the bottom surface can be soldered by the dip method. When chip components or flat pack ICs are soldered to the top surface of the board, and components with lead wires are soldered to the bottom surface, without inverting the board 10. , can be done at the same time.

発明の効果 以上の通り本発明によると、透孔の上面では全周の一部
に半田ランド部を形成し、その上に導電体を半田付けす
ることにより、半田が透孔へ流下することが抑制され、
信頼性の高い半田付けを行うことができる。これは半田
付けをリフローで行う時に特に有効となる。
Effects of the Invention As described above, according to the present invention, a solder land portion is formed on a part of the entire circumference of the upper surface of the through hole, and a conductor is soldered thereon, thereby preventing solder from flowing down into the through hole. suppressed,
Highly reliable soldering can be performed. This is particularly effective when soldering is performed by reflow.

その導電体の他端を透孔へ挿通し、透孔の反対面では全
周に形成した半田ランド部に半田付けしても、その導電
体の一端は透孔の全周の一部に形成した半田ランド部に
半田付けされ、透孔が閉塞されることがなく、フラック
ス等のガスをスムーズに逃がすことができ、信頼性の高
い両面半田付けが可能であり、スルーホールと同様の機
能を有するものを安価に提供できる。
Even if the other end of the conductor is inserted into the through hole and soldered to the solder land formed around the entire circumference on the opposite side of the through hole, one end of the conductor is formed only on a part of the entire circumference of the through hole. It is soldered to the solder land part that has been soldered, the through hole is not blocked, gas such as flux can escape smoothly, and highly reliable double-sided soldering is possible, and it has the same function as a through hole. We can provide what we have at low cost.

導電体の両端を隣接する2個の透孔に挿通し、半田付け
する場合、両端で必要に応じて基板両面の導電箔の間を
半田付けすることができ、基板両面間で半田付けできる
導電箔の数を増すことができ、実装密度を高めることが
できる。
When inserting both ends of a conductor into two adjacent through holes and soldering, it is possible to solder between the conductive foils on both sides of the board at both ends as necessary, and the conductor can be soldered between both sides of the board. The number of foils can be increased and the packaging density can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は第1図A
部拡大平面図、第3図は従来例の断面図、第4図は第3
図A部拡大平゛面図である。 10・・・絶縁性基板、 13.14・・・透孔、 37拳・O半田ランド部、 39.20・@拳半田うンド部、 21・・・導電体、 22・拳・一端部、 23・・・他端部。 第1 図 第2図
Figure 1 is a sectional view of one embodiment of the present invention, and Figure 2 is Figure 1A.
3 is a sectional view of the conventional example, and FIG. 4 is a sectional view of the conventional example.
It is an enlarged plan view of part A of the figure. 10...Insulating board, 13.14...Through hole, 37. Fist/O solder land part, 39.20/@fist solder land part, 21... Conductor, 22. Fist/one end part, 23...Other end. Figure 1 Figure 2

Claims (11)

【特許請求の範囲】[Claims] (1)絶縁性基板と、該絶縁性基板に穿設された透孔と
、該透孔の上面の孔周囲の一部に形成された半田ランド
部と、該半田ランド部上に延びた導電体と、前記半田ラ
ンド部と前記導電体との間を接続する半田とから成るプ
リント基板。
(1) An insulating substrate, a through hole drilled in the insulating substrate, a solder land portion formed in a part of the periphery of the hole on the upper surface of the through hole, and a conductive portion extending over the solder land portion. A printed circuit board comprising a body and solder connecting between the solder land portion and the conductor.
(2)請求項(1)において、前記半田による接続はリ
フロー半田付け法により行われるプリント基板の製造方
法。
(2) The method for manufacturing a printed circuit board according to claim (1), wherein the solder connection is performed by a reflow soldering method.
(3)絶縁性基板と、該絶縁性基板に穿設された透孔と
、該透孔の表面と裏面に形成された半田ランド部とから
成るプリント基板において、前記透孔の表面と裏面に形
成された半田ランド部の一方は、前記透孔の周囲の全部
又は一部に形成されており、他方は前記透孔の周囲の一
部に形成されていることを特徴とするプリント基板。
(3) In a printed circuit board consisting of an insulating substrate, a through hole formed in the insulating substrate, and a solder land portion formed on the front and back surfaces of the through hole, the front and back surfaces of the through hole are A printed circuit board characterized in that one of the formed solder land portions is formed in all or part of the periphery of the through hole, and the other is formed in a part of the periphery of the through hole.
(4)請求項(3)において、前記透孔の周囲の一部は
、前記透孔の周囲の約半分に形成されていることを特徴
とするプリント基板。
(4) The printed circuit board according to claim (3), wherein a portion of the periphery of the through hole is formed to be approximately half of the periphery of the through hole.
(5)前記透孔には導体が挿通され、該導体は前記透孔
の表面と裏面に形成された半田ランド部に半田付けされ
ている請求項(1)又は(2)のプリント基板。
(5) The printed circuit board according to claim 1 or 2, wherein a conductor is inserted through the through hole, and the conductor is soldered to solder land portions formed on the front and back surfaces of the through hole.
(6)請求項(5)において、前記導体の一端は前記透
孔に隣接して前記絶縁性基板に穿設された他の透孔へ延
出されており、該他の透孔の表面又は裏面に形成された
他の半田ランド部に、他の半田を介して接続されている
ことを特徴とするプリント基板。
(6) In claim (5), one end of the conductor extends to another through hole bored in the insulating substrate adjacent to the through hole, and the surface of the other through hole or A printed circuit board characterized in that the printed circuit board is connected to another solder land portion formed on the back surface via another solder.
(7)絶縁性基板と、該絶縁性基板に所定距離だけ離し
て穿設された2個の透孔と、前記絶縁性基板の裏面で前
記2個の透孔の各々の周囲の全部に形成された半田ラン
ド部と、前記絶縁性基板の表面で前記2個の透孔の少な
くとも一方の周囲の一部分に形成された半田ランド部と
から成るプリント基板。
(7) an insulating substrate, two through holes bored a predetermined distance apart in the insulating substrate, and holes formed all around each of the two through holes on the back surface of the insulating substrate; and a solder land portion formed in a portion around at least one of the two through holes on the surface of the insulating substrate.
(8)請求項(7)において、前記2個の透孔の一方に
一端部が挿通され他方に他端部が挿通され中間部が前記
2個の透孔に跨がって配置された導電線と、前記導電線
の一端部と他端部を前記透孔の各々の周囲の全部に形成
された半田ランド部に夫々接続させる半田と、前記導電
線の中間部を前記2個の透孔の少なくとも一方の周囲の
一部分に形成された半田ランド部に接続させる半田とか
ら成るプリント基板。
(8) In claim (7), one end of the conductor is inserted into one of the two through holes, the other end is inserted through the other of the two through holes, and the intermediate portion is disposed astride the two through holes. a wire, solder for connecting one end and the other end of the conductive wire to solder lands formed all around each of the through holes, and a middle portion of the conductive wire connected to the two through holes. and solder connected to a solder land portion formed on a portion of at least one periphery of the printed circuit board.
(9)請求項(7)において、前記導電線の中間部を半
田で接続させる前記2個の透孔の少なくとも一方の周囲
の一部分に形成された半田ランド部は、該2個の透孔の
一方の周囲の一部分が、前記導電線の中間部の延出した
側の一部分であることを特徴とするプリント基板。
(9) In claim (7), a solder land portion formed in a part of the periphery of at least one of the two through holes to which the intermediate portions of the conductive wires are connected by solder is a solder land portion formed around at least one of the two through holes. A printed circuit board characterized in that a portion of one periphery is a portion of an extended side of the intermediate portion of the conductive wire.
(10)請求項(5)において、前記導体が前記透孔の
表面に形成された半田ランド部にリフロー半田付け法に
より半田付けされ、又前記導体が前記透孔の裏面に形成
された半田ランド部にディップ半田付け法により半田付
けされることを特徴とするプリント基板。
(10) In claim (5), the conductor is soldered to a solder land formed on the surface of the through hole by reflow soldering, and the conductor is soldered to a solder land formed on the back surface of the through hole. A printed circuit board characterized in that the parts are soldered by a dip soldering method.
(11)請求項(8)において、透孔の周囲の全部に形
成された半田ランド部にディップ半田付け法により半田
付けされ、又透孔の周囲の一部分に形成されることを特
徴とするプリント基板の製法。
(11) In claim (8), the print is soldered by dip soldering to a solder land portion formed entirely around the through hole, and is also formed on a part of the periphery of the through hole. Substrate manufacturing method.
JP18521888A 1988-07-25 1988-07-25 Printed board and manufacture thereof Pending JPH0234988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18521888A JPH0234988A (en) 1988-07-25 1988-07-25 Printed board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18521888A JPH0234988A (en) 1988-07-25 1988-07-25 Printed board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0234988A true JPH0234988A (en) 1990-02-05

Family

ID=16166945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18521888A Pending JPH0234988A (en) 1988-07-25 1988-07-25 Printed board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0234988A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5324450B2 (en) * 1976-09-20 1978-07-20
JPS5939962B2 (en) * 1977-02-10 1984-09-27 株式会社東芝 electric vehicle control device
JPS6025172B2 (en) * 1975-12-24 1985-06-17 エコダイン コ−ポレ−シヨン liquid cooling tower

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6025172B2 (en) * 1975-12-24 1985-06-17 エコダイン コ−ポレ−シヨン liquid cooling tower
JPS5324450B2 (en) * 1976-09-20 1978-07-20
JPS5939962B2 (en) * 1977-02-10 1984-09-27 株式会社東芝 electric vehicle control device

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