JPS6240462Y2 - - Google Patents
Info
- Publication number
- JPS6240462Y2 JPS6240462Y2 JP1982009907U JP990782U JPS6240462Y2 JP S6240462 Y2 JPS6240462 Y2 JP S6240462Y2 JP 1982009907 U JP1982009907 U JP 1982009907U JP 990782 U JP990782 U JP 990782U JP S6240462 Y2 JPS6240462 Y2 JP S6240462Y2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- electronic component
- conductor layer
- printed circuit
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 34
- 239000000853 adhesive Substances 0.000 claims description 26
- 230000001070 adhesive effect Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 13
- 238000013022 venting Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 22
- 238000005476 soldering Methods 0.000 description 5
- 238000007872 degassing Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- -1 resistors Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】
本考案は、例えばコンデンサ、抵抗、半導体等
の電子部品がマウントされるプリント基板に関
し、特に、簡単な構成で空気やガスによる気泡の
滞留を防止し半田付着の信頼性を著しく向上させ
得るようにしたプリント基板に関するものであ
る。[Detailed description of the invention] The present invention relates to printed circuit boards on which electronic components such as capacitors, resistors, semiconductors, etc. are mounted, and in particular prevents the accumulation of bubbles due to air and gas with a simple configuration and improves the reliability of solder adhesion. This invention relates to a printed circuit board that can significantly improve the performance.
一般に、この種のプリント基板は、リード線を
有しないチツプ状の電子部品の両端に設けた電極
部を、ランドと称されている導体層に樹脂製接着
剤等を用いて仮止めした状態で、直接半田デツプ
法により半田付けして形成される。 Generally, this type of printed circuit board has electrode parts provided at both ends of a chip-shaped electronic component that does not have lead wires, temporarily fixed to a conductor layer called a land using a resin adhesive or the like. , formed by soldering using a direct solder dip method.
ところで、電子部品を基板上に接着剤等で仮固
定した状態で、その基板を半田槽の溶融半田に浸
漬すると、溶融された半田が電子部品の両端側に
流れ込むため、その流れによつて空気が一緒にそ
の流れに巻き込まれる一方、半田からのフラツク
ス等が高温にさらされて一部がガス化することが
ある。このような空気やガスが発生すると、電子
部品の両端と基板との間にそれら空気やガスによ
る気泡が滞留することとなる。そのため、これら
空気や気泡が半田の濡れを邪摩し半田付着の信頼
性を著しく阻害するような欠点があつた。 By the way, when an electronic component is temporarily fixed on a board with an adhesive or the like, and the board is immersed in molten solder in a solder tank, the molten solder flows to both ends of the electronic component, and the flow causes air to escape. While the flux from the solder is exposed to high temperatures, some of it may gasify. When such air or gas is generated, bubbles caused by the air or gas remain between both ends of the electronic component and the substrate. Therefore, these air and bubbles interfere with wetting of the solder, resulting in a drawback that the reliability of solder adhesion is significantly impaired.
また、電子部品の両端に設けた電極部を一対の
導体層に半田デイツプする際、基板上に電子部品
を仮固定するための接着剤が溶けて一対の導体層
上面を覆つてしまい、そのため良好な半田が行な
えない欠点があつた。 Additionally, when soldering the electrodes provided at both ends of an electronic component onto a pair of conductor layers, the adhesive used to temporarily fix the electronic component on the board melts and covers the top surface of the pair of conductor layers, resulting in poor performance. There was a drawback that soldering was not possible.
本考案は、このような従来の欠点を除去し得る
プリント基板を提案するものである。 The present invention proposes a printed circuit board that can eliminate these conventional drawbacks.
以下、本考案の一実施例を図面に従つて説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本考案に係るプリント基板P1の要部を
示す正面断面図、第２図は同じくプリント基板P1
の要部を示す右側断面図、第３図は同じくプリン
ト基板P1の要部を示す一部破断平面図である。 Fig. 1 is a front sectional view showing the main parts of the printed circuit board P 1 according to the present invention, and Fig. 2 is a front sectional view showing the main parts of the printed circuit board P 1 according to the present invention.
FIG. 3 is a partially cutaway plan view showing the main parts of the printed circuit board P1 .
第１図ないし第３図に示すように、基板１上に
は、例えばコンデンサ、抵抗、半導体等の各種の
電子部品２を一体的に接合するための接着剤３の
塗布領域４を間に挟んで、少なくとも一対の導体
層（一般にランドと称されている。）５，６がそ
の基板１上に対向して形成されている。 As shown in FIGS. 1 to 3, on a substrate 1, a coating area 4 of an adhesive 3 for integrally bonding various electronic components 2 such as capacitors, resistors, semiconductors, etc. is sandwiched between them. At least a pair of conductor layers (generally called lands) 5 and 6 are formed on the substrate 1 to face each other.
これら各導体層５，６のうち、少なくとも一つ
の導体層（この実施例では両方の導体層）５，６
の電子部品２の取付側位置で、かつ、それらの各
導体層５，６の一部にかかる位置には、貫通孔
７，８がそれぞれ形成されている。これら各貫通
孔７，８は、ガス抜きと接着剤流出防止という２
つの目的を同時に満足させるために設けられたも
のである。 Among these conductor layers 5, 6, at least one conductor layer (both conductor layers in this embodiment) 5, 6
Through-holes 7 and 8 are respectively formed at positions on the mounting side of the electronic component 2 and over a portion of each of the conductor layers 5 and 6. These through holes 7 and 8 have two functions: gas venting and adhesive leakage prevention.
It was established to satisfy two purposes at the same time.
すなわち、これら各貫通孔７，８を形成したの
は、電子部品２を基板１上に接着剤３で仮固定し
た状態で、その基板１を半田槽内の溶融された半
田に浸漬した際に発生するフラツクス等によるガ
スや空気等を第１図及び第２図中矢印Ａ方向に放
出させるためと、半田デイツプの際に溶けた接着
剤３が一対の導体層５，６の上面まで流出しその
上面を覆つてしまうことがないように、溶けた接
着剤３の一部３ａ，３ｂをその貫通孔７，８内に
導くことにより、その流出を防止するためという
２つの働きを同時に満たすようにするためであ
る。 That is, the through holes 7 and 8 were formed when the electronic component 2 was temporarily fixed on the board 1 with the adhesive 3 and the board 1 was immersed in molten solder in a solder bath. In order to release gas, air, etc. due to flux etc. generated in the direction of arrow A in FIGS. By guiding parts 3a and 3b of the melted adhesive 3 into the through holes 7 and 8 so as not to cover the upper surface thereof, the two functions of preventing the adhesive from flowing out are fulfilled at the same time. This is for the purpose of
上記電子部品２の各電極部９，１０と各導体層
５，６との間には、それらを一体的に接合するた
めの半田１１，１２が半田デイツプ法によつて付
着されている。 Solders 11 and 12 are attached between each electrode portion 9 and 10 of the electronic component 2 and each conductor layer 5 and 6 by a solder dip method for integrally joining them.
なお、この実施例では、各導体層５，６と直交
するように、各貫通孔７，８の間の接着剤塗布領
域４上には、クロスパターン部１３，１４が形成
されている。 In this embodiment, cross pattern parts 13 and 14 are formed on the adhesive application area 4 between the through holes 7 and 8 so as to be perpendicular to the conductor layers 5 and 6.
以上のような構成を有する本考案の作用につい
て説明する。 The operation of the present invention having the above configuration will be explained.
まず、一対の導体層５，６に電子部品２の電極
部９，１０が位置するように、その電子部品２を
接着剤３上に載置し、その接着剤３で基板１上に
電子部品２を仮固定しておく。 First, the electronic component 2 is placed on the adhesive 3 so that the electrode parts 9 and 10 of the electronic component 2 are located on the pair of conductor layers 5 and 6, and the electronic component 2 is placed on the substrate 1 using the adhesive 3. Temporarily fix 2.
次に、電子部品２を下側にして、所要の半田槽
の溶融半田内に浸漬する。このとき、電子部品２
の電極部９，１０と基板１との間には、溶融半田
の流れに伴う空気あるいはフラツクス等に起因し
てガスによる気泡が生ずることがあるが、このよ
うな場合でも、一対の導体層５，６にかかる位置
であつて各電極部９，１０に対応する位置には一
対の貫通孔７，８がそれぞれ形成されているの
で、その貫通孔７を通して第１図及び第２図中矢
印Ａ方向に放出される。従つて、電極部９，１０
と導体層５，６との間に付着される半田１１，１
２中に空気や気泡が滞留するようなことはない。
そのため、各導体層５，６への各電極部９，１０
の半田付けの信頼性を著しく向上させることがで
きる。 Next, the electronic component 2 is immersed in molten solder in a desired solder tank with the electronic component 2 facing downward. At this time, electronic component 2
Gas bubbles may be generated between the electrode portions 9 and 10 of the substrate 1 and the substrate 1 due to air or flux accompanying the flow of molten solder. , 6 and corresponding to the respective electrode parts 9, 10, a pair of through holes 7, 8 are formed, respectively, so that the arrow A in FIGS. 1 and 2 is inserted through the through holes 7. emitted in the direction. Therefore, the electrode parts 9, 10
and the conductor layers 5, 6.
There is no possibility that air or bubbles will remain inside the tube.
Therefore, each electrode part 9, 10 to each conductor layer 5, 6
The reliability of soldering can be significantly improved.
また、上述した半田デイツプの際に、溶融され
た半田の熱により接着剤３の一部が溶けて各導体
層５，６側に流出しても、各導体層５，６の電子
部品取付側位置には、上述した貫通孔７，８が形
成されているので、その貫通孔７，８内にその接
着剤３の一部３ａ，３ｂは流れ込み、決して各導
体層５，６の上面に流出することがない。従つ
て、各電極部９，１０の各導体層５，６への半田
付け状態が接着剤流出により阻害されるようなこ
とがなく、良好な導通状態を確保することができ
る。 In addition, even if a part of the adhesive 3 melts due to the heat of the melted solder and flows out to the side of each conductor layer 5, 6 during the solder dip described above, the side of each conductor layer 5, 6 where the electronic components are mounted Since the above-mentioned through holes 7 and 8 are formed in the positions, parts 3a and 3b of the adhesive 3 flow into the through holes 7 and 8, and never flow out onto the upper surface of each conductor layer 5 and 6. There's nothing to do. Therefore, the soldering state of each electrode part 9, 10 to each conductor layer 5, 6 is not hindered by adhesive leakage, and a good conductive state can be ensured.
次に、第４図ないし第６図は本考案の他の実施
例を示したものであり、この実施例では、上記実
施例と異なり、角柱状の電子部品２ａを基板１上
にマウントしてプリント基板P2を形成した場合に
ついて示している。 Next, FIGS. 4 to 6 show another embodiment of the present invention. In this embodiment, unlike the above embodiment, a prismatic electronic component 2a is mounted on the substrate 1. A case is shown in which a printed circuit board P2 is formed.
第４図ないし第６図に示すように、基板１上に
は、例えばコンデンサ、抵抗、半導体等の角柱状
の各種の電子部品２ａを一体的に接合するための
接着剤３の塗布領域４を間に挟んで、少なくとも
一対の導体層５，６がその基板１上に対向して形
成されている。 As shown in FIGS. 4 to 6, on the substrate 1, there is a coating area 4 of an adhesive 3 for integrally bonding various prismatic electronic components 2a such as capacitors, resistors, semiconductors, etc. At least a pair of conductor layers 5 and 6 are formed facing each other on the substrate 1, sandwiched therebetween.
これら各導体層５，６のうち、少なくとも一つ
の導体層（この実施例では両方の導体層）７ａ，
８ａの電子部品２ａの取付側位置で、かつ、それ
らの各導体層５，６の一部にかかる位置には、貫
通孔７ａ，８ａがそれぞれ形成されている。これ
ら各貫通孔７ａ，８ａは、上記実施例と同様、ガ
ス抜きと接着剤流出防止という２つの目的を同時
に満足させるために設けられたものである。これ
ら各貫通孔７ａ，８ａは、上記実施例と異なり、
電子部品２ａの両端に設けた電極部９ａ，１０ａ
によりその貫通孔７ａ，８ａの一端開口部７ｂ，
８ｂが完全に閉塞されないように、上記電極部９
ａ，１０ａの両側壁部分よりも第４図及び第６図
中左右方向に出る位置まで貫通形成されている。 Among these conductor layers 5 and 6, at least one conductor layer (both conductor layers in this embodiment) 7a,
Through-holes 7a and 8a are formed at positions 8a on the mounting side of the electronic component 2a and over a portion of each of the conductor layers 5 and 6, respectively. These through-holes 7a, 8a are provided to simultaneously satisfy the two purposes of degassing and preventing adhesive from flowing out, as in the above embodiment. These through holes 7a, 8a are different from the above embodiment,
Electrode parts 9a and 10a provided at both ends of the electronic component 2a
One end opening 7b of the through hole 7a, 8a,
8b is not completely occluded.
It is formed to penetrate to a position that extends in the left-right direction in FIGS. 4 and 6 from both side wall portions of portions a and 10a.
このような構成にプリント基板P2を形成した場
合には、基板１上に角形状の電子部品２ａをマウ
ントするときでも、貫通孔７ａ，８ａの一端開口
部７ｂ，８ｂが電子部品２ａの電極部９ａ，１０
ａで完全に閉塞されることはない。従つて、半田
デイツプ時において生ずる気泡や空気を各貫通孔
７ａ，８ａを通して外部（基板１上部）に放出さ
せることができる。 When the printed circuit board P 2 is formed in such a configuration, even when the rectangular electronic component 2a is mounted on the substrate 1, the openings 7b and 8b at one end of the through holes 7a and 8a are connected to the electrodes of the electronic component 2a. Parts 9a, 10
It is not completely occluded by a. Therefore, bubbles and air generated during solder dipping can be released to the outside (upper part of the substrate 1) through the through holes 7a and 8a.
基板上に電子部品を仮固定するための接着剤が
塗布される接着剤塗布領域を間に挟んで少なくと
も一対の導体層を相対向させて形成するととも
に、上記導体層の一部にかかる位置であつて上記
導体層に接続される上記電子部品の電極部に対応
する位置にガス抜き兼接着剤流出防止用の貫通孔
を形成したものであるから、半田デイツプ時に発
生する空気や気泡を上記貫通孔を介して放出し、
且つ導体層間に塗布される接着剤を上記貫通孔で
吸収し上記導体層側への流出を防止し得るので、
電子部品の電極部と導体層間を半田による確実な
接続を保証できるので、上記電極部と導体層間の
電気導通を確実になし得るとともに機械的な接続
強度を充分に保証し得るものとなる。 At least a pair of conductor layers are formed facing each other with an adhesive application area sandwiched therebetween, where an adhesive for temporarily fixing electronic components is applied to the substrate, and at a position covering a part of the conductor layer. Since a through hole is formed at a position corresponding to the electrode part of the electronic component connected to the conductor layer to vent gas and prevent adhesive from flowing out, air and bubbles generated during solder dipping can be passed through the hole. released through the pores,
In addition, the adhesive applied between the conductor layers can be absorbed by the through holes and prevented from flowing out to the conductor layer side.
Since a reliable connection by solder can be guaranteed between the electrode part and the conductor layer of the electronic component, electrical continuity between the electrode part and the conductor layer can be ensured, and mechanical connection strength can be sufficiently guaranteed.
特に、本考案は、ガス抜き兼接着剤流出防止用
の貫通孔を、電子部品の電極部が接続される導体
層にかかる位置であつて上記電極部に対応する位
置に形成するものであるから、半田デイツプ時に
最もガスが発生しやすい位置に上記貫通孔が設け
られることになり、一層確実なガス抜き効果を達
成し得る。 Particularly, in the present invention, a through hole for degassing and preventing the adhesive from flowing out is formed at a position corresponding to the electrode part of the electronic component and across the conductor layer to which the electrode part is connected. Since the through hole is provided at a position where gas is most likely to be generated during solder dipping, a more reliable degassing effect can be achieved.
第１図は本考案に係るプリント基板の一実施例
を示す要部正面断面図、第２図は上記第１図に示
したプリント基板の同図中のＩ−Ｉ線における右
側断面図、第３図は上記第１図に示したプリント
基板の要部を示す一部破断平面図である。第４図
は本考案に係るプリント基板の他の実施例を示す
要部正面断面図、第５図は上記第４図に示したプ
リント基板の同図中の−線における右側断面
図、第６図は上記第４図に示したプリント基板の
要部を示す一部破断平面図である。
１……基板、２，２ａ……電子部品、３……接
着剤、４……塗布領域、５，６……導体層、７，
８，７ａ，８ａ……ガス抜き兼接着剤流出防止用
の貫通孔、９，１０，９ａ，１０ａ……各電極
部、１１，１２……半田。
FIG. 1 is a front cross-sectional view of essential parts showing an embodiment of a printed circuit board according to the present invention, FIG. 2 is a right cross-sectional view of the printed circuit board shown in FIG. FIG. 3 is a partially cutaway plan view showing the main parts of the printed circuit board shown in FIG. 1 above. FIG. 4 is a front sectional view of main parts showing another embodiment of the printed circuit board according to the present invention, FIG. 5 is a right sectional view of the printed circuit board shown in FIG. This figure is a partially cutaway plan view showing the main parts of the printed circuit board shown in FIG. 4 above. 1... Board, 2, 2a... Electronic component, 3... Adhesive, 4... Application area, 5, 6... Conductor layer, 7,
8, 7a, 8a...Through hole for degassing and preventing adhesive outflow, 9, 10, 9a, 10a...Each electrode part, 11, 12...Solder.
Claims (1)
塗布される接着剤塗布領域を間に挟んで少なくと
も一対の導体層を相対向させて形成するととも
に、上記導体層の一部にかかる位置であつて上記
導体層に接続される上記電子部品の電極部に対応
する位置にガス抜き兼接着剤流出防止用の貫通孔
を形成してなるプリント基板。 At least a pair of conductor layers are formed facing each other with an adhesive application area sandwiched therebetween, where an adhesive for temporarily fixing electronic components is applied to the substrate, and at a position covering a part of the conductor layer. A printed circuit board comprising a through hole for venting gas and preventing adhesive from flowing out at a position corresponding to an electrode portion of the electronic component connected to the conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP990782U JPS58114070U (en) | 1982-01-29 | 1982-01-29 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP990782U JPS58114070U (en) | 1982-01-29 | 1982-01-29 | Printed board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114070U JPS58114070U (en) | 1983-08-04 |
| JPS6240462Y2 true JPS6240462Y2 (en) | 1987-10-16 |
Family
ID=30022512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP990782U Granted JPS58114070U (en) | 1982-01-29 | 1982-01-29 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114070U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013004651A (en) * | 2011-06-15 | 2013-01-07 | Panasonic Corp | Print wiring board, and motor or electrical equipment including the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5530838A (en) * | 1978-08-24 | 1980-03-04 | Matsushita Electric Ind Co Ltd | Method of mounting chip part |
| JPS5525313B2 (en) * | 1975-11-12 | 1980-07-04 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5525313U (en) * | 1978-08-02 | 1980-02-19 | ||
| JPS5696670U (en) * | 1979-12-21 | 1981-07-31 |
-
1982
- 1982-01-29 JP JP990782U patent/JPS58114070U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5525313B2 (en) * | 1975-11-12 | 1980-07-04 | ||
| JPS5530838A (en) * | 1978-08-24 | 1980-03-04 | Matsushita Electric Ind Co Ltd | Method of mounting chip part |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58114070U (en) | 1983-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5001605A (en) | Multilayer printed wiring board with single layer vias | |
| US5574629A (en) | Solderless printed wiring devices | |
| JPS6240462Y2 (en) | ||
| JPH0548262A (en) | Composite hybrid integrated circuit | |
| JPH11103145A (en) | Circuit board and surface mounting component | |
| JPH0821764B2 (en) | Printed board | |
| JPH0878850A (en) | Printed wiring board | |
| JP3735858B2 (en) | Soldering structure of parts to printed circuit board | |
| JPS6120791Y2 (en) | ||
| JPH0311903Y2 (en) | ||
| JPS6236316Y2 (en) | ||
| JPH0455360B2 (en) | ||
| JP2501678Y2 (en) | Circuit board device | |
| JP3226147B2 (en) | Bonding structure of surface mount components | |
| JP2002026482A (en) | Mounting structure of electronic component | |
| JP3696921B2 (en) | Soldering jig and electronic component mounting substrate manufacturing method | |
| JP2002374060A (en) | Electronic circuit board | |
| JPH0535589B2 (en) | ||
| JPS6127200Y2 (en) | ||
| JP3346215B2 (en) | Printed wiring board and manufacturing method thereof | |
| JPH073661Y2 (en) | Printed board | |
| JPH088510A (en) | Leadless chip carrier | |
| JPH0536302Y2 (en) | ||
| JPS63133695A (en) | Printed wiring board | |
| JPH03262186A (en) | Printed wiring board |