JPH02336A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02336A JPH02336A JP30521688A JP30521688A JPH02336A JP H02336 A JPH02336 A JP H02336A JP 30521688 A JP30521688 A JP 30521688A JP 30521688 A JP30521688 A JP 30521688A JP H02336 A JPH02336 A JP H02336A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor circuit
- migration
- metal
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000005012 migration Effects 0.000 abstract description 17
- 238000013508 migration Methods 0.000 abstract description 17
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にマイグレーションによ
り生じる金属配線の断線及びマイグレーションの進行を
チエツクするチェックパターンを備えた半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a check pattern for checking metal wiring breakage caused by migration and progress of migration.
従来、半導体デバイスにおける、マイグレーションによ
る金属配線の断線及びマイグレーションの進行のチエツ
クは、半導体デバイス内の配線自体をチエツクすること
によって行われていた。Conventionally, in a semiconductor device, checking for disconnection of metal wiring due to migration and progress of migration has been performed by checking the wiring itself within the semiconductor device.
上述した従来のチエツク方法では、半導体デバイス内の
配線自体をチエツクすることになるので、発見が困難で
あり、また製造工程中では、マイグレーションの進行を
加速させた条件でチエツクすることなども不可能であり
、製造条件とマイグレーションの関係を調査するのに多
大な時間を要した。さらに、信頼性試験を行う場合にお
いても、半導体デバイス内にマイグレーションに対して
故意に悪くなるようなパターンがないため、試験に長時
間を要していた。The conventional checking method described above involves checking the wiring itself within the semiconductor device, which makes it difficult to detect, and it is also impossible to check under conditions that accelerate the progress of migration during the manufacturing process. Therefore, it took a lot of time to investigate the relationship between manufacturing conditions and migration. Furthermore, even when conducting a reliability test, the test takes a long time because there is no pattern in the semiconductor device that is intentionally bad for migration.
本発明の目的は、このような問題を解決し、半導体デバ
イス内に故意にマイグレーションを加速する形状となる
チェックパターンを設けることにより、マイグレーショ
ンを効率的にチエツクできるようにした半導体装置を提
供することにある。An object of the present invention is to solve such problems and provide a semiconductor device in which migration can be efficiently checked by providing a check pattern in a semiconductor device with a shape that intentionally accelerates migration. It is in.
本発明の半導体装置の構成は、半導体回路を形成する基
板上にこの半導体回路の配線と同一の金属によってこの
半導体回路と電気的に独立して配設された金属配線を備
え、かつこと金属配線の一部にくさび状のくびれ部を、
このくびれ部の線幅が前記半導体回路の最小配線幅と同
等かもしくはそれ以下となるような形状にしたチェック
パターンとして形成し、かつこのチェックパターンが互
いに直角となるように2つ配置されていることを特徴と
する。The structure of the semiconductor device of the present invention includes a metal wiring disposed on a substrate forming a semiconductor circuit, made of the same metal as the wiring of the semiconductor circuit, and electrically independent of the semiconductor circuit. A wedge-shaped constriction in a part of the
A check pattern is formed in such a shape that the line width of the constriction is equal to or less than the minimum wiring width of the semiconductor circuit, and two check patterns are arranged at right angles to each other. It is characterized by
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の部分平面図である。FIG. 1 is a partial plan view of one embodiment of the present invention.
本実施例は、半導体基板等の上に配設されたAj2もし
くはAA系合金により構成される金属配線10がその一
部分にくさび形のくさび部11を有し、このパターンが
実際の半導体回路の配線方向にあわせて、互いに直角な
2方向にあることを特徴とする。本実施例のマイグレー
ションチエツク用のパターンは、半導体デバイスの配線
に用いられる金属配線10)こより形成され、電気的に
この半導体デバイスの配線と独立した配線で構成され、
この配線の一部にその幅がデバイス内の最小線幅と同等
か、それ以下となるようなくびれ部11となっている。In this embodiment, a metal wiring 10 made of Aj2 or AA alloy disposed on a semiconductor substrate etc. has a wedge-shaped wedge part 11 in a part thereof, and this pattern is similar to the wiring of an actual semiconductor circuit. It is characterized by being located in two directions that are perpendicular to each other. The migration check pattern of this embodiment is formed from metal wiring 10) used for wiring of a semiconductor device, and is composed of wiring that is electrically independent from the wiring of this semiconductor device.
A part of this wiring has a constricted portion 11 whose width is equal to or less than the minimum line width within the device.
このくびれ部11によって、金属配線10のチェックパ
ターンに引張り応力が働いた場合には、くびれ部11の
部分に応力集中が起こりやすくなり、この部分に特にス
トレスマイグレーションが起こりやすくなる。また電流
を流した場合にはくびれ部で電流密度が最も高くなる。When tensile stress is applied to the check pattern of the metal wiring 10 due to the constricted portion 11, stress concentration tends to occur in the constricted portion 11, and stress migration is particularly likely to occur in this portion. Furthermore, when a current is applied, the current density is highest at the constriction.
従って、この部分を観測することにより、マイグレーシ
ョンを加速した状態でチエツクすることができる。Therefore, by observing this part, it is possible to check migration in an accelerated state.
第2図は本発明の第2の実施例の部分平面図である。本
実施例は、基板上のAAもしくはAl系合金により構成
される金属配線10の一部分配線の一方の側だけにくび
れ部12を有している。このくびれ部12にも応力集中
が発生するような形状となっているため、この部分を観
察することにより、加速してマイグレーションのチエツ
クをすることができる。FIG. 2 is a partial plan view of a second embodiment of the invention. In this embodiment, a narrow portion 12 is provided only on one side of a partial wiring of a metal wiring 10 made of AA or Al-based alloy on a substrate. Since this constricted portion 12 is also shaped so that stress concentration occurs, by observing this portion, it is possible to check for accelerated migration.
実施例2では、実施例1より加速の度合がややおちるが
、マスク作成上はより容易であるという利点がある。In Example 2, although the degree of acceleration is slightly lower than in Example 1, it has the advantage of being easier to create a mask.
以上説明したように本発明は、マイグレーションに対し
て最悪状態もしくは加速された状態となるような形状を
チェックパターン上にあらかじめ設けておくことにより
、半導体デバイスのマイグレーションチエツクを効果的
に行うことができる。As explained above, the present invention can effectively perform a migration check of a semiconductor device by providing in advance on a check pattern a shape that is in the worst state or accelerated state with respect to migration. .
第1図Figure 1
第1図、第2図は本発明の第1および第2の実施例を示
す部分平面図である。
10・・・・・・AAもしくはAi7系合金より構成さ
れる金属配線、11.12・・・・・・くびれ部。
代理人 弁理士 内 原 音
第z図1 and 2 are partial plan views showing first and second embodiments of the present invention. 10... Metal wiring made of AA or Ai7 alloy, 11.12... Constriction. Agent Patent Attorney Uchihara Sound Diagram Z
Claims (1)
と同一の金属によってこの半導体回路と電気的に独立し
て配設された金属配線を備え、かつこの金属配線の一部
にくさび状のくびれ部を、このくびれ部の線巾が前記半
導体回路の最小配線幅と同等かもしくはそれ以下となる
ような形状にしたチェックパターンとして形成し、かつ
このチェックパターンが互いに直角となるように2つ配
置されていることを特徴とする半導体装置。A substrate forming a semiconductor circuit is provided with a metal wiring made of the same metal as the wiring of the semiconductor circuit and arranged electrically independently of the semiconductor circuit, and a part of the metal wiring has a wedge-shaped constriction. The part is formed as a check pattern such that the line width of the constricted part is equal to or less than the minimum wiring width of the semiconductor circuit, and two check patterns are arranged so as to be perpendicular to each other. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63305216A JP2590553B2 (en) | 1987-12-07 | 1988-12-01 | Semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-310163 | 1987-12-07 | ||
JP31016387 | 1987-12-07 | ||
JP63305216A JP2590553B2 (en) | 1987-12-07 | 1988-12-01 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02336A true JPH02336A (en) | 1990-01-05 |
JP2590553B2 JP2590553B2 (en) | 1997-03-12 |
Family
ID=26564212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63305216A Expired - Lifetime JP2590553B2 (en) | 1987-12-07 | 1988-12-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2590553B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04321251A (en) * | 1991-04-22 | 1992-11-11 | Sharp Corp | Manufacture of semiconductor device |
JP2012174773A (en) * | 2011-02-18 | 2012-09-10 | Toshiba Corp | Semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52139383A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Testing method for semiconductor device |
JPS5583247A (en) * | 1978-12-20 | 1980-06-23 | Hitachi Ltd | Electron migration detector |
JPS5637659A (en) * | 1979-09-04 | 1981-04-11 | Nec Corp | Semiconductor device |
JPS5848933A (en) * | 1981-08-28 | 1983-03-23 | Fujitsu Ltd | Large scale integrated circuit with monitor function |
JPS6283677A (en) * | 1985-10-08 | 1987-04-17 | Nec Corp | Apparatus for testing electromigration |
-
1988
- 1988-12-01 JP JP63305216A patent/JP2590553B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52139383A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Testing method for semiconductor device |
JPS5583247A (en) * | 1978-12-20 | 1980-06-23 | Hitachi Ltd | Electron migration detector |
JPS5637659A (en) * | 1979-09-04 | 1981-04-11 | Nec Corp | Semiconductor device |
JPS5848933A (en) * | 1981-08-28 | 1983-03-23 | Fujitsu Ltd | Large scale integrated circuit with monitor function |
JPS6283677A (en) * | 1985-10-08 | 1987-04-17 | Nec Corp | Apparatus for testing electromigration |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04321251A (en) * | 1991-04-22 | 1992-11-11 | Sharp Corp | Manufacture of semiconductor device |
JP2012174773A (en) * | 2011-02-18 | 2012-09-10 | Toshiba Corp | Semiconductor device |
US8723331B2 (en) | 2011-02-18 | 2014-05-13 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2590553B2 (en) | 1997-03-12 |
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