JPS63151032A - Lead of semiconductor device - Google Patents

Lead of semiconductor device

Info

Publication number
JPS63151032A
JPS63151032A JP61299430A JP29943086A JPS63151032A JP S63151032 A JPS63151032 A JP S63151032A JP 61299430 A JP61299430 A JP 61299430A JP 29943086 A JP29943086 A JP 29943086A JP S63151032 A JPS63151032 A JP S63151032A
Authority
JP
Japan
Prior art keywords
lead
width
stress
region
ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61299430A
Other languages
Japanese (ja)
Inventor
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61299430A priority Critical patent/JPS63151032A/en
Publication of JPS63151032A publication Critical patent/JPS63151032A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make it possible to form a lead, which is not broken even if stress is applied to a substrate, by providing a region, which is broader than the width of the lead, in the middle of the lead, and providing a hole in the broad region. CONSTITUTION:An electrode 2 of a semiconductor element 1, which is mounted by a film carrier method, is connected to a lead 3. The lead 3 has a broad area 4 at the intermediate part of the lead. A hole 5 is provided, and the so- called ring shaped lead 4 is provided. The lead 3 is bonded to a wiring pattern 6 of a wiring substrate 7 with alloy, soldering and the like. A width C of the lead is larger than a width A of the lead. The width B of the lead is approximately the same size as the width A of the lead. Since the ring shaped lead region is provided, stress applied on the lead is absorbed by the extension of the ring. Thus the fracture of the lead can be prevented. When the stress acts on the wiring substrate and the lead itself, the broad region of the lead, i.e., the ring shaped lead part, is elongated, and the stress is absorbed. Therefore such a defect as the fracture of the lead does not occur.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子の電極と回路基板の配線パターン間
を接続するのに用いる半導体装置のリードの構成に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a lead of a semiconductor device used to connect between an electrode of a semiconductor element and a wiring pattern of a circuit board.

従来の技術 第６図で従来の技術を説明する。半導体素子１０の電極
１１には例えばフィルムキャリヤ方式によりＣｕ箔で形
成したリード１２が形成され、このリード１２を介して
半導体素子１０は配線基板１３上の配線パターン１４に
接合されている。Prior Art The conventional technology will be explained with reference to FIG. A lead 12 made of Cu foil is formed on the electrode 11 of the semiconductor element 10, for example, by a film carrier method, and the semiconductor element 10 is connected to a wiring pattern 14 on a wiring board 13 via this lead 12.

いわゆるフィルムキャリヤ方式による半導体素子を配線
基板に搭載する場合である。This is a case where a semiconductor element is mounted on a wiring board using a so-called film carrier method.

発明が解決しようとする問題点 ところが、このような構成にあっては、第７図の如く配
線基板１３に熱や機械的応力によって、伸びの応力１５
が作用したとすると、この応力は少なくともリード１２
に引張り力を与える。この応力によって、リード１２は
伸びて応力に耐えようとするが、わずか３６μｍ厚さで
、巾５０〜１ｏＯμｍのＣｕ箔では、この応力に耐えき
れず第７図すの如く、遂にはリード１２を破損してしま
う結果になっていた。Problems to be Solved by the Invention However, in such a configuration, as shown in FIG.
is applied, this stress is at least on the lead 12.
gives a tensile force to. Due to this stress, the lead 12 tries to elongate and withstand the stress, but the Cu foil, which is only 36 μm thick and 50 to 100 μm wide, cannot withstand this stress and the lead 12 eventually breaks down as shown in Figure 7. This resulted in damage.

特に配線基板が可撓性を有する基板である場合や、半導
体素子の入力端子と出力端子が各々別の配線基板に接続
固定される場合には、このようなリードの破断する不良
は割合高い確率で発生していた。Particularly when the wiring board is a flexible board, or when the input and output terminals of a semiconductor element are connected and fixed to different wiring boards, there is a high probability that such lead breakage failures will occur. It was occurring in

本発明は、配線基板に応力が作用してもリードが破断し
ない、リードの構成を提供するものである。The present invention provides a lead structure in which the leads do not break even when stress is applied to the wiring board.

問題点を解決するための手段 本発明はリードに応力が作用した場合、これを吸収する
ために、リードの途中にリング状の構成を設けたもので
、リードの途中にリードの巾よシも巾広の領域を設け、
この巾広の領域内に孔を設けたリードの構成であ°る。Means for Solving the Problems The present invention provides a ring-shaped structure in the middle of the lead in order to absorb stress when it is applied to the lead, and a ring-shaped structure is provided in the middle of the lead to reduce the width of the lead. Set up a wide area,
The lead has a hole in this wide area.

作用 リードに応力が作用し、リードに引張力が作用したとす
ると、孔を有する巾広の領域すなわちリング状のリード
は、このリングをリードの長手方向に押拡げる状態に変
形し、リードに作用した応力を吸収することになる。If stress is applied to the acting reed and a tensile force is applied to the reed, the wide region with holes, that is, the ring-shaped reed, deforms to a state where the ring is pushed out in the longitudinal direction of the reed, and this acts on the reed. This will absorb the stress caused by the

実施例 第１図で本発明の詳細な説明する。Example The present invention will be explained in detail with reference to FIG.

フィルムキャリヤ方式で実装された半導体素子１の電極
２はリード３の途中で巾広の領域４を有し、かつ孔６を
有する、いわゆるリング状のリード４が設けられ、リー
ド３は配線基板７の配線パターン６に合金や半田づけ等
により接合されている。・ 前記リング状のリード４は、少なくとも半導体素子１の
電極２とリードとの接合部と配線基板７の配線パターン
６とリードとの接合部との間のリードに構成される。The electrode 2 of the semiconductor element 1 mounted by the film carrier method is provided with a so-called ring-shaped lead 4 having a wide region 4 and a hole 6 in the middle of the lead 3, and the lead 3 is connected to the wiring board 7. It is joined to the wiring pattern 6 by alloying, soldering, etc. - The ring-shaped lead 4 is configured as a lead between at least the joint between the electrode 2 of the semiconductor element 1 and the lead and the joint between the wiring pattern 6 of the wiring board 7 and the lead.

更にリードの形状例について詳述する。第２図ａにおい
てリード巾Ｃはリード巾広よシも大きい。Furthermore, examples of lead shapes will be described in detail. In FIG. 2a, the lead width C is also larger than the lead width.

またリード巾Ｂはリード巾広とほぼ同一の寸法である。Further, the lead width B is approximately the same dimension as the lead width.

例えばリード中入が１００μｍ、リード巾Ｃが３００μ
ｍ、リード巾Ｂが１００μｍに設計した場合の構成にあ
っては、第２図すの如く上下方向にリードに応力が作用
すれば、前記リング状の領域は、上下方向に押拡げられ
、リード全体が丁度自由に伸びることになる。初期の巾
広領のリードの寸法ｘ１　に対し、リードに応力が加わ
って、リードが切断する直前の、前記リードの巾広領域
の伸びた寸法ｘ２はｘｌの約２．５倍であった。すなわ
ちｘｌが１００μｍだから２５０μｍまでリードが伸び
て応力を吸収した事になる。この様にリードの途中にリ
ング状のリード領域を設けることによシリードに加わっ
た応力をリングが伸びる事によって吸収し、リードの破
断を防止できるものである。For example, the lead depth is 100μm and the lead width C is 300μm.
m, in a configuration where the lead width B is designed to be 100 μm, if stress is applied to the lead in the vertical direction as shown in Figure 2, the ring-shaped region is expanded in the vertical direction, and the lead The whole thing will stretch freely. With respect to the initial dimension x1 of the wide region of the lead, the extended dimension x2 of the wide region of the lead immediately before the lead was cut due to stress being applied to the lead was about 2.5 times xl. In other words, since xl is 100 μm, the lead extends to 250 μm and absorbs stress. By providing a ring-shaped lead region in the middle of the lead in this way, the stress applied to the lead can be absorbed by the expansion of the ring, thereby preventing breakage of the lead.

リング状部分のリードの形状は第３図の如くリードと直
角方向に長孔を有するものであっても良いし、この場合
、応力をより多く吸収し、リードの伸び量が多い。また
第４図の如く斜め方向に長孔を有するものであっても本
発明の効果を得る事ができるものである。The shape of the lead in the ring-shaped portion may have a long hole in the direction perpendicular to the lead as shown in FIG. 3, and in this case, more stress is absorbed and the lead elongates more. Furthermore, the effects of the present invention can be obtained even with a device having elongated holes in an oblique direction as shown in FIG.

リング状リードの配列についてのべれば、第６図ａの如
くリング状の領域が横一列に配設された構成であっても
良いし、第６図すの如くリング状の領域を千鳥状に配設
することもできる。この様な千鳥状に配設したリードに
おいては、お互いのリード間隔を狭くすることができる
から狭ピッチのリードに対応できる。Regarding the arrangement of the ring-shaped leads, the ring-shaped areas may be arranged in a horizontal row as shown in Figure 6a, or the ring-shaped areas may be arranged in a staggered manner as shown in Figure 6. It can also be placed in In such leads arranged in a staggered manner, the distance between the leads can be narrowed, so that it is possible to accommodate leads with a narrow pitch.

発明の効果 以上のように、本発明によれば、配線基板やリード自体
に応力が作用した場合、リードの巾広領域すなわちリン
グ状のリード部分が伸びて、これら応力を吸収するので
、リードの破断という不良発生がない。Effects of the Invention As described above, according to the present invention, when stress is applied to the wiring board or the leads themselves, the wide area of the leads, that is, the ring-shaped lead portion, expands and absorbs the stress. There are no defects such as breakage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のリードを示す斜視図、第２
図は同リードの形状の寸法を示す平面図、第３図、第４
図は本発明の他の実施例におけるす−ドの形状を示す平
面図、第６図はリードの配設状態を示す平面図、第６図
は従来のリードの斜視図、第７図は同リードが破断する
過程を示した断面図である。 １・・・・・・半導体素子、３・・・・・・リード、４
・・・・・・巾広のリード、６・・・・・・孔、６・・
・・・・配線パターン、７・・・・・・配線基板。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名／−
−−手導体宗子 第２図 Ｃ”　　　　　　　　　　　　（ｂ） 箔３図　　　　　第４図 第５図 （の 第６図 第７図FIG. 1 is a perspective view showing a lead according to an embodiment of the present invention, and FIG.
The figures are a plan view showing the dimensions of the shape of the lead, Figures 3 and 4.
6 is a plan view showing the arrangement of the leads, FIG. 6 is a perspective view of the conventional lead, and FIG. 7 is the same. FIG. 3 is a cross-sectional view showing a process in which a lead breaks. 1... Semiconductor element, 3... Lead, 4
...Wide reed, 6...hole, 6...
...Wiring pattern, 7...Wiring board. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Te conductor Muneko 2nd figure C" (b) Foil 3rd figure 4th figure 5th figure 6th figure 7th figure

Claims (5)

【特許請求の範囲】[Claims] （１）半導体素子の電極から延在し、回路基板の配線パ
ターンと接続するフィルムリードであって、前記半導体
素子の電極と配線パターンの接合部間のフィルムリード
の一部分が巾広領域を有し、かつ前記巾広の領域内に孔
を有してなる半導体装置のリード。(1) A film lead extending from an electrode of a semiconductor element and connected to a wiring pattern of a circuit board, wherein a part of the film lead between the joint part of the electrode of the semiconductor element and the wiring pattern has a wide area. , and having a hole in the wide region. （２）巾広の領域と孔とで形成されるリードの巾が、巾
広以外の領域の巾と同一もしくは、小さい特許請求の範
囲第１項記載の半導体装置のリード。(2) A lead for a semiconductor device according to claim 1, wherein the width of the lead formed by the wide region and the hole is the same as or smaller than the width of the non-wide region. （３）孔の形状がリードの巾と直角方向に長孔である特
許請求の範囲第１項記載の半導体装置のリード。(3) A lead for a semiconductor device according to claim 1, wherein the hole has an elongated shape in a direction perpendicular to the width of the lead. （４）リードが巾広の領域以外の領域で回路基板の配線
パターンに接続される特許請求の範囲第１項記載の半導
体装置のリード。(4) A lead for a semiconductor device according to claim 1, wherein the lead is connected to a wiring pattern of a circuit board in an area other than the wide area. （５）半導体素子の電極から導出される複数のリードの
巾広い領域が配列方向において千鳥状に配置されている
特許請求の範囲第１項記載の半導体装置のリード。(5) A lead for a semiconductor device according to claim 1, wherein the wide regions of the plurality of leads led out from the electrodes of the semiconductor element are arranged in a staggered manner in the arrangement direction.
JP61299430A 1986-12-16 1986-12-16 Lead of semiconductor device Pending JPS63151032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61299430A JPS63151032A (en) 1986-12-16 1986-12-16 Lead of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61299430A JPS63151032A (en) 1986-12-16 1986-12-16 Lead of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63151032A true JPS63151032A (en) 1988-06-23

Family

ID=17872468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61299430A Pending JPS63151032A (en) 1986-12-16 1986-12-16 Lead of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63151032A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5102084A (en) * 1989-10-16 1992-04-07 Hyundai Electronics Ind. Co., Ltd. Positioning apparatus with gears and a pivot for angularly and longitudinally positioning the screen of a lap top computer
US5109572A (en) * 1989-09-23 1992-05-05 Hyundai Electronics Ind. Co., Ltd. Locking hinge device for the LCD screen of a word processor
US5570505A (en) * 1993-11-16 1996-11-05 International Business Machines Corporation Method of manufacturing a circuit module
US7961454B2 (en) 2005-05-18 2011-06-14 Sanyo Electric Co., Ltd. Multi-layered solid electrolytic capacitor and method of manufacturing same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5109572A (en) * 1989-09-23 1992-05-05 Hyundai Electronics Ind. Co., Ltd. Locking hinge device for the LCD screen of a word processor
US5102084A (en) * 1989-10-16 1992-04-07 Hyundai Electronics Ind. Co., Ltd. Positioning apparatus with gears and a pivot for angularly and longitudinally positioning the screen of a lap top computer
US5570505A (en) * 1993-11-16 1996-11-05 International Business Machines Corporation Method of manufacturing a circuit module
US7961454B2 (en) 2005-05-18 2011-06-14 Sanyo Electric Co., Ltd. Multi-layered solid electrolytic capacitor and method of manufacturing same

Similar Documents

Publication Publication Date Title
US6558560B2 (en) Method for the fabrication of electrical contacts
KR980005659A (en) Semiconductor device and manufacturing method thereof
JPS63151032A (en) Lead of semiconductor device
US5408127A (en) Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components
KR19980086909A (en) Printed Board
US5153705A (en) Tab package and a liquid-crystal panel unit using the same
JPH0519982B2 (en)
JPH04196253A (en) Package for semiconductor device
JP2005123569A (en) Method of mounting wafer on printed wiring substrate
TW497232B (en) Semiconductor device and method of manufacturing the same
JPH0823148A (en) Connecting structure for circuit board
JPS6132821B2 (en)
JP6063669B2 (en) Electronic device and method for manufacturing electronic device
KR950008849B1 (en) Semiconductor and manufacture method
KR100267517B1 (en) Structure of bonding an inner lead to an electrode in a semiconductor device
JP4973488B2 (en) Semiconductor device
JP6205031B2 (en) Electronic device and method for manufacturing electronic device
JP2001094000A (en) Semiconductor device
JPS63164331A (en) Film carrier lead
JPS5815297A (en) Printed circuit board
JPH077165U (en) Circuit board
JPH02178957A (en) Semiconductor device
JPH11214832A (en) Formation of plating wire in circuit board
JPH1140925A (en) Method of electrolytic plating of plastic circuit board
JP2009302200A (en) Film for cof, semiconductor device, and production method of film for cof