JPH11214832A - Formation of plating wire in circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect unplated parts of external input/output terminals and component mounting sections, by connecting the external input/output terminals and the component mounting sections by plating wires with a cut line which should be divided into each circuit board put between, and allowing current to flow in one path from one side to the other in each of a plurality of groups of divided sections to be plated. SOLUTION: A region to be plated is divided into an upper group 12a and a lower group 12b by cutting a part of a plating wire or snake wire 16. In each group, current is caused to flow in one direction and, if the group is broken at one place, plating does not progress for the rest of the group. In the wire for plating, current flows in one direction and there is no double conduction. Therefore, even if the wire has defects on the way, the defects can be easily detected by the existence of an unplated section. Furthermore, a variation in length of plating wires can be supported in wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plated wire on a circuit board, and more particularly to a method for forming a plated wire capable of suppressing variation in the length of the plated wire.

More specifically, according to the present invention, external input / output terminals and / or component mounting portions of a circuit board for mounting electronic components such as a ball grid array (BGA) substrate and a chip carrier are made of Ni / Au. The present invention relates to a method for forming a plated wire of a circuit board suitable for performing electrolytic plating.

[0003]

2. Description of the Related Art In a type of plastic package for electronic components such as ICs and LSIs, electronic components are mounted on a plastic circuit board instead of a lead frame, and a resin is injected into the mounting portion and sealed. There is something.

The plastic package used for this plastic package is made of a rigid film made of a composite material such as glass fiber / epoxy resin or glass fiber / phenol resin, and a flexible film made of a heat-resistant resin such as polyimide resin. Have been.

[0005] This type of plastic package can have the same structure as a ceramic package.
A (pin grid array), BGA (sometimes called ball grid array, bump grid array), LG
A (land grid array) or the like is used. Among them, a BGA (that is, a multi-terminal structure that can be used without using pins and is applicable to a flexible plastic circuit board) is used.
(pBGA) is attracting attention.

As in the case of a printed wiring board, a circuit is formed on a plastic substrate by laminating copper foil on both surfaces of the plastic substrate and etching away unnecessary portions of the copper foil by photolithography using a photoresist. . Before that, if necessary, a through hole is formed in the plastic substrate by drilling, and the wall surface of the through hole is covered with a copper film by copper plating (normally, the copper layer is thickened by electrolytic plating after electroless plating). .

A circuit portion used for electrical connection including electrode portions on both surfaces of the plastic circuit board thus formed.
(Hereinafter, these are referred to as external input / output terminals and / or component mounting portions) are easily oxidized when copper is used, and the conductivity is reduced. Therefore, gold plating is applied to protect the external input / output terminals and / or component mounting portions. . The external input / output terminals and / or component mounting portions are, on the surface side on which the electronic component is mounted, a wire bonding portion used for electrical connection with the electronic component or an electrode pad portion in the case of flip chip connection. On the back side, it is an electrode pad section connected to the motherboard.

[0008] Gold plating is 2.5
A plating film without pinholes cannot be obtained unless the thickness is as thick as 5 μm, but if Ni plating is applied to the base, the corrosion resistance is remarkably improved, so that the gold plating can be thinned. In order to reduce the amount of expensive gold used, it is common to use Ni / Au plating in which the base is plated with Ni.

In this Ni / Au plating, a solder resist is screen-printed on a plastic substrate, a portion other than a portion to be plated is covered with the solder resist, and a plating film having an appropriate thickness can be obtained by a single plating operation. It is done by law. Thereafter, holes for alignment are made around the substrate by punching and / or a router, and then inspected, packaged, and shipped.

Further, in chip carriers (including a quartz oscillator case), there is a type in which an electronic component is mounted on a ceramic package, and a sealing cap is later attached and sealed. Also in this chip carrier, usually
Although a tungsten material is used for the electrode portion, a portion used for electrical connection, that is, an external input / output terminal and a component mounting portion are subjected to Ni / Al plating to be mountable.

As shown in FIG. 1, the chip carrier 10 comprises:
In general, a plurality of (eg, 4 to 8) substrates are manufactured in a state called a “series” 12 in which one or more rows are connected in a row. The user mounts a plurality of electronic components (not shown) on each chip carrier 10 in the state of the ream 12 at a time, then seals the mounting portion of each electronic component, and finally cuts or cuts into individual chip carriers. Break. Thereby, the work efficiency is greatly improved as compared with the case where one chip carrier is handled.

[0012]

In order to apply Ni / Au electrolytic plating to external input / output terminals and / or component mounting portions on both surfaces of such a large number of circuit boards such as ceramic chip carriers, all external input / output Terminals and / or component mounting parts need to be connected to an external power supply. In FIG. 1, the wiring section from the electrode section (not shown) to the input / output terminal section is shown.
Only 14 is shown.

For this reason, as shown in FIG. 2, conventional techniques such as squid wiring 16 (staggered wiring) and the like are used, and the input / output terminals 14 of each electrode portion are plated simultaneously with the streaks 12 at the same time. As shown in FIG. 3, by breaking or cutting the ream 12 into a single product 20, the sleeky wiring 16 is divided.

However, in this method, the wiring 16
However, because it surrounds the outer circumference of the end of each circuit board, it is a double / triple plated wire, and conduction can be taken from many directions. However, even if it is cut off, conduction is obtained due to the shining wiring wrapping around from other parts, and plating is applied to such a portion, and even a defective product is determined to be a good product.

Here, a general object of the present invention is to provide a method for electrolytic plating a circuit board which does not require a tie bar between adjacent circuit boards. Further, a more specific object of the present invention is to provide a plating wire for a circuit board such as a BGA board or a chip carrier, which can easily detect a portion where an external input / output terminal to be plated and / or a component mounting portion is not plated. Is to provide a method for forming

[0016]

The inventor of the present invention has proposed that the slick wiring for plating be formed on a required plating portion of each circuit board from a single location so as to be capable of conducting. I focused on doing.

Further, in order to balance the plating,
Divide the conventional shining wiring in the middle so that the total length of each plating wire is as same as possible, divide the plating area into a plurality of areas, and take conduction from only one direction in each. By doing so, the inventors have found that the above-mentioned problem can be effectively solved, and have completed the present invention.

Here, the present invention relates to a method for electroplating external input / output terminals and / or component mounting portions of a plurality of circuit boards connected to each other, the adjacent external input / output terminals to be plated and / or The component mounting section is connected to each circuit board by a plating line across a cutting line to be divided, and the external input / output terminals and / or the component mounting section connected by the plating line are divided into a plurality of groups. hand,
A method for forming a plated wire on a circuit board, characterized in that each group conducts conduction from one side to the other side in one path.

According to the embodiment of the present invention, when the external input / output terminals and / or component mounting parts are divided into a plurality of groups as described above, the lengths of the plating wires in each group are as equal as possible. Is preferred. It is preferable that the number of groups is as small as possible from the viewpoint of improving work efficiency.

As described above, according to the present invention, each group of plating regions conducts only in one direction, and therefore, if there is even a broken portion in any one portion, the group in the group further includes a broken portion. It can be easily visually identified without plating.

Also, instead of using a tie bar to connect a lead line, for example, a plated line, adjacent lead lines are connected to each other with a dedicated line as a plated line, and cut such that the dedicated line is disconnected when a series or each circuit board is cut. By doing so, at least a part of the tie bar can be omitted.

Unlike a ceramic circuit board, when a plastic circuit board is used, four lead lines of the circuit board are often provided at different positions. This is because the output ball pad portion of the package, in particular, the signal line ball pad portion which needs to take out the lead wire as a plating wire one by one is arranged at an arbitrary position and has no symmetry.

Therefore, the lead lines are not always continuous between the circuit boards adjacent in the vertical or horizontal direction, and the lead lines corresponding to the lead lines existing on one circuit board are connected to the adjacent circuit boards. If it does not exist on the board but ends at the outer peripheral edge of one circuit board, a lead wire that exists only on one circuit board is extended to the other circuit board with a dedicated line, and this extension is performed. The installation portion may be connected to the lead wires on both sides (or extension portions thereof) by the dedicated connection line as described above. In that case, the connection on one side does not necessarily need to be made to straddle the cut portion, but may be made only in the other extended circuit board.

[0024]

FIG. 4 illustrates a method of forming a plated wire according to the present invention. In FIG. 4, a plated wire, that is, a shining wiring portion 16 is partially cut at, for example, "x" locations. Therefore, the plating area is the upper row 12a in the illustrated example.
And the lower row 12b are divided into two sections, and both of them are conducted from one direction, so that any breakage at any one place prevents plating from being performed further.

By doing so, the wiring for plating is
Current flows from one direction, and double conduction is eliminated.
Therefore, even if there is a defect (such as a disconnection) in the wiring in the middle, such a defect can be easily found due to the presence of the unplated portion.

Further, the present invention can be applied not only to the manufacture of a series of circuit boards, but also to electrolytic plating in the manufacture of a single circuit board. For a single circuit board,
The method for connecting a lead wire to an adjacent circuit board according to the present invention is as follows.
Although it is preferable to apply to all the lead lines of the substrate, it may be applied to only some of them.

The circuit board such as a chip carrier used in the method of the present invention is not particularly limited as long as it has heat resistance, insulation and other properties required for a ceramic circuit board. Typical examples are polyimide resins other than ceramics, especially addition-polymerized polyimide resins (eg, BT resin)
However, a composite material such as a glass fiber-containing epoxy resin can also be used.

The type of the circuit board used in the method of the present invention is not particularly limited. The preferred type is a chip carrier, but the method of the present invention can be applied to electrolytic plating of an electrode portion of another plastic circuit board such as pBGA, pPGA, and pLGA.

In the electrolytic plating method of the present invention, the lead wire for current supply connected to each electrode, that is, the plating wire is connected by another dedicated wire, and when the lead wire is not a “continuous lead wire”, The lead wire is extended to the adjacent substrate with a dedicated line. The formation of the dedicated lines can be performed simultaneously with the formation of the electrodes and the lead lines. In the case of a plastic substrate, electrodes and lead lines are formed by etching away specific portions of copper foil laminated on both sides of a plastic sheet (blank) by photolithography technology, and connect the lead lines at that time A dedicated line and a lead wire extension can be formed at the same time. That is, the above-described dedicated line can be formed simultaneously with the electrode and the lead-out line by simply changing the shape of the photomask to be used and without adding an extra step.

Similarly, for a ceramic substrate (chip carriers), it is only necessary to change the shape of the printing photomask. The electrolytic plating itself in the method of the present invention may be performed in the same manner as in the related art. The plating metal type of the electrolytic plating is not particularly limited, but the electrode portions of the plastic circuit board and the ceramic circuit board are generally plated with Ni / Au. That is, first, electrolytic Ni plating and then electrolytic Au plating are performed.

After plating is completed, cutting is performed at a predetermined cutting position to obtain a single-piece plastic circuit board or ceramic circuit board. As a result of this cutting, the dedicated line formed across the cutting position is cut, and as a result, the lead wires as plating lines are electrically insulated from each other on both of the adjacent substrates.

[0032]

EXAMPLE In this example, the present invention was implemented using a plastic chip carrier as a circuit board.

As shown in FIG. 5, a chip (not shown) in a chip carrier 50 is formed by a wire bonding method or the like.
Wiring to the input / output terminals on the outer periphery of the chip carrier 50 (A)
Are wirings necessary for this chip carrier. Incidentally, the solid line (B) is a boundary line of the chip carriers 50 when the chip carriers 50 are arranged in an array, that is, a place where the chip carriers 50 are cut or broken in a later step. In the drawings, reference numerals 52 and 54 denote edge castellations of the external input / output terminals, respectively. Reference numeral 56 denotes a hole for forming a corner inverted R shape of the singulated substrate. However, in this state, plating cannot be performed on these wirings.

Therefore, in FIG. 6, a sliver wiring for plating is added so that plating is applied to the wiring requiring plating. The symbol (C) indicates a slick wiring.

In this case, from four directions, i, b, c and d,
Even if a plated wire is formed and the portion of the wiring (D) necessary for the chip carrier 50 is broken, the wiring before and after the portion is plated except for that portion. In the part (E), as shown in FIG. 7, the part of the wiring (D) is broken, and even if the continuity is not obtained from the plated wires A, C, and D, the plating is sunk (B). Since the continuity is established, the wiring (E) of the chip carrier 50 is plated and the disconnection cannot be recognized.

Therefore, according to the present invention, the chip carrier 50
In the case where the wiring required by (1) is broken, the plating wire lead-out is improved so that plating is not applied. This will be described with reference to FIG. Wiring (Each b, b,
Are divided into four groups of (c) and (d), each of which has conduction in one-way path, and is not connected to each other.

Therefore, for example, as shown in FIG. 9, if the wiring (D) is broken, the external wiring terminal (E) connected to the external input / output terminal connected to the plating wire ahead of the wiring including that part is connected. Since no plating is applied to the component mounting portion, the defect can be easily determined visually.

[0038]

According to the present invention, since the double wiring of the plating wire is eliminated, if the wiring required by the chip carrier is broken for any reason, plating on the chip carrier is necessary. Since no plating is attached to such a location, a defective product can be visually identified.

[Brief description of the drawings]

FIG. 1 is a schematic view of a series of chip carriers.

FIG. 2 is a schematic view in which a shining line for plating is added to the series of FIG. 1;

FIG. 3 is a schematic view of one circuit board when the series of FIG. 2 is cut into individual circuit boards and individualized.

FIG. 4 is a schematic view when the double wiring of the plating wire is eliminated according to the present invention.

FIG. 5 is an enlarged view of a corner of the substrate of FIG. 1;

FIG. 6 is an enlarged view of a corner of the board when shining wiring is further added in FIG. 5;

FIG. 7 is an enlarged view of FIG. 6 with a partial disconnection.

FIG. 8 is a schematic diagram when the double wiring of the plating wire is eliminated according to the present invention.

FIG. 9 is a schematic diagram when a part of a wiring (D) is cut off in FIG.

Claims (1)

[Claims] When electroplating external input / output terminals and / or component mounting portions of a plurality of circuit boards connected to each other, adjacent external input / output terminals and / or component mounting portions to be plated on each circuit board are connected to each other. The external input / output terminals and / or component mounting parts connected by the plating lines are divided into a plurality of groups while connecting the cutting lines to be divided to the respective circuit boards with the plating lines therebetween. A method of forming a plated wire on a circuit board, wherein conduction is established from one to another by a single path.