JPH023250A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPH023250A JPH023250A JP14994688A JP14994688A JPH023250A JP H023250 A JPH023250 A JP H023250A JP 14994688 A JP14994688 A JP 14994688A JP 14994688 A JP14994688 A JP 14994688A JP H023250 A JPH023250 A JP H023250A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- plane
- gaas
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 150000001875 compounds Chemical class 0.000 title claims description 42
- 239000004065 semiconductor Substances 0.000 title claims description 42
- 239000013078 crystal Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910021480 group 4 element Inorganic materials 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 41
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 6
- 230000005684 electric field Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010793 electronic waste Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は極めて高速の移動度を有する電子を用いた化合
物半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a compound semiconductor device using electrons having extremely high mobility.
（従来の技術）
従来、この種の化合物半導体装置として、高純度層と、
該高純度層より広い禁制帯幅を有する電子供給層を接合
させた場合、高純度層内に二次元的に極めて移動度の高
い電子を含む電子層が生じることを利用した電界効果型
トランジスタか知られている。この電界効果型トランジ
スタでは、大きな移動度を持つ高濃度二次元電子によっ
て高い相互コンダクタンスを実現できることか報告され
ている。(Prior art) Conventionally, this type of compound semiconductor device has a high purity layer,
A field-effect transistor that utilizes the fact that when an electron supply layer having a wider forbidden band width than the high-purity layer is bonded, an electron layer containing two-dimensionally extremely high-mobility electrons is generated within the high-purity layer. Are known. It has been reported that this field-effect transistor can achieve high mutual conductance using highly concentrated two-dimensional electrons with large mobility.
一方、電子を線状に、即ち、−次元的に閉じ込めること
ができれば、二次元的な電子層よりも、電子密度を高く
でき、相互コンダクタンスを更に高くできるものと考え
られる。しかしながら、従来の技術では、電子を一次元
的に閉じ込めることは非常に困難である。On the other hand, if electrons can be confined linearly, that is, in a -dimensional manner, it is thought that the electron density can be made higher than in a two-dimensional electron layer, and the mutual conductance can be made even higher. However, with conventional techniques, it is extremely difficult to confine electrons one-dimensionally.
（発明が解決しようとする課題）
本発明は、従来の化合物半導体装置に比べより高い相互
コンダクタンスを得ることができる化合物半導体装置を
提供することである。(Problems to be Solved by the Invention) An object of the present invention is to provide a compound semiconductor device that can obtain higher mutual conductance than conventional compound semiconductor devices.
本発明の池の目的は高濃度の電子を線状に閉じ込めて一
次元電子層を形成できる化合物半導体装置を提供するこ
とを課題とする。An object of the present invention is to provide a compound semiconductor device that can form a one-dimensional electron layer by linearly confining highly concentrated electrons.
（課題を解決するための手段）
本発明は、極めて細い線状の（ＯＯ’１ ）面と、該（
００１）面を境界を接する（１１１）Ｂ方位面を露出さ
せた高純度層を用い、前記（００１）面には高純度層よ
り、も広い禁制帯幅を有する第１の化合物半導体結晶に
よって形成された電子供給層を形成する一方、（１１１
）面上に電子供給層に対して同等以上の禁制帯幅を有す
る第２の化合物半導体結晶を形成した化合物半導体装置
が得られる。(Means for Solving the Problems) The present invention provides an extremely thin linear (OO'1) plane and the (OO'1) plane.
A high-purity layer in which a (111)B-oriented plane bordering the (001) plane is exposed is used, and the (001) plane is formed of a first compound semiconductor crystal having a wider bandgap than the high-purity layer. (111
) A compound semiconductor device is obtained in which a second compound semiconductor crystal having a forbidden band width equal to or larger than that of the electron supply layer is formed on the surface.
（作 用）
本発明によれば、第１の化合物半導体結晶から、高純度
層に流入した電子は、それをとり囲むように形成された
（１１１）８面上の広い禁制帯幅を有する層によって両
側から閉じこめられて、実効的に細い線状の一次元電子
層となる。この−次元電子層を用いて相互コンダクタン
スの大きい電界効果型トランジスタを構成することがで
きる。(Function) According to the present invention, electrons flowing into the high-purity layer from the first compound semiconductor crystal are transferred to the layer having a wide forbidden band width on the (111) 8 plane formed so as to surround it. The electrons are confined from both sides, effectively forming a thin linear one-dimensional electron layer. A field effect transistor with high mutual conductance can be constructed using this -dimensional electronic layer.
以下、図面を参照して本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.
（実施例１）
第１図を参照すると、本発明の一実施例に係る化合物半
導体装置は下地としてのＧａＡｓ層１゜を有し、このＧ
ａＡｓ層１０は高純度層を形成している。ＧａＡｓ層１
０の表面には、第１の方位面として、＜００１）面１１
が線状に、即ち、次元的に露出されており、且つ、＜０
０１）面１１の両側に、（００１）面１１と境界を接す
るように設けられた第２の方位面としての（１１１）８
面１２が露出されている。ここで、ＧａＡ・８層１０は
ＧａＡｓ基板であってもよく、また、エピタキ・シャル
成長層であってもよい、この関係で、ＧａＡｓ層１０は
Ｉ［［−Ｖ族化合物半導体領域と呼ばれてもよい、上記
した互いに異なる方位面を露出させることはＧａＡｓ層
１０を通常の選択エツチングにより可能である。(Example 1) Referring to FIG. 1, a compound semiconductor device according to an example of the present invention has a GaAs layer of 1° as a base, and this G
The aAs layer 10 forms a high purity layer. GaAs layer 1
0 has the <001) plane 11 as the first azimuth plane.
is exposed linearly, that is, dimensionally, and <0
01) (111) 8 as a second azimuth plane provided on both sides of the plane 11 so as to border the (001) plane 11
Surface 12 is exposed. Here, the GaA 8 layer 10 may be a GaAs substrate or may be an epitaxially grown layer. In this relationship, the GaAs layer 10 is called an I[[-V group compound semiconductor region. The GaAs layer 10 can be exposed by ordinary selective etching to expose the above-mentioned mutually different oriented planes.
次に、（００１）面１１上に、電子供給層として第１の
ＡｊＧａＡｓ層１６を成長させると共に、（１１１）８
面１２上に第２のＡＪＧａＡｓ層１７を成長させる。こ
こで、第１及び第２のＡｊＧａＡｓ層１６及び１７には
、不純物としてケイ素（Ｓｉ）が添加されており、これ
らＡｊＧａＡｓ層１６及び１７はＧａＡｓ層１０より広
い禁制帯を有している。Next, the first AjGaAs layer 16 is grown as an electron supply layer on the (001) plane 11, and the (111)8
A second AJGaAs layer 17 is grown on surface 12. Here, silicon (Si) is added as an impurity to the first and second AjGaAs layers 16 and 17, and these AjGaAs layers 16 and 17 have a wider forbidden band than the GaAs layer 10.
通常、＜００１）面１１上の［［−Ｖ族化合物半導体に
添加したケイ素はドナーとなり、ｎ型ドーパントとして
働くが、（１１１）８面１２上の■Ｖ族化合物半導体に
添加した場合、アクセプタとなり、ｐ型ドーパントとし
て働くことが知られている。Usually, silicon added to the [[-V group compound semiconductor on the <001) plane 11 becomes a donor and acts as an n-type dopant, but when silicon is added to the ■V group compound semiconductor on the (111)8 plane 12, it becomes an acceptor. It is known that it acts as a p-type dopant.
また、高温でＡＪＧａＡｓ層を形成する場合、同一成長
条件下であっても、（１１１）８面１２では（００１）
面１１に比べて、Ｇａ原子の脱離量が多く、結果として
、（１１１）８面１２には、（００１）面１１よりもＡ
１組成の高いＡＪＧａＡｓ層が形成されることか判明し
た。このことは、同一条件で生成された第１及び第２の
Ａｊ ＧａＡｓ層１６及び１７のうち、（１１１）８面
１２上に形成された第２のＡｊＧａＡｓ層１７は（００
１）面１１上に形成された第１のＡＮ ＧａＡｓ層１６
に比べて広い禁制帯幅を有していることになる。In addition, when forming an AJGaAs layer at high temperature, even under the same growth conditions, (111)8 plane 12 has (001)
Compared to the plane 11, the amount of desorption of Ga atoms is larger, and as a result, the (111)8 plane 12 has more A atoms than the (001) plane 11.
It was found that an AJGaAs layer having a high composition of 1 was formed. This means that among the first and second Aj GaAs layers 16 and 17 produced under the same conditions, the second Aj GaAs layer 17 formed on the (111)8 plane 12 has a (00
1) First AN GaAs layer 16 formed on surface 11
This means that the forbidden band width is wider than that of .
以上述べた構成では、（００１）面１１上には、ＧａＡ
ｓ層１０より広い禁制帯幅を有する第１のＡＮ ＧａＡ
ｓ層（ｎ型ＡＪＧａＡｓ層）１６が形成され、ＧａＡｓ
層１０とへテロ接合をなし、ＧａＡｓ層１０中に電子カ
ス層（以下、単に、電子層と呼ぶ）２０を生成する。ま
た、（１１１）８面１２上には、第１のＡＪＧａＡｓ層
１６より更に禁制帯幅の広い第２のＡＪＧａＡｓ層＜ｐ
型ＡｊＧａＡｓ層）１７が形成されている。In the configuration described above, on the (001) plane 11, GaA
First AN GaA having a wider forbidden band width than the s-layer 10
An s layer (n-type AJGaAs layer) 16 is formed, and GaAs
It forms a heterojunction with the layer 10 and generates an electronic waste layer (hereinafter simply referred to as an electronic layer) 20 in the GaAs layer 10. Further, on the (111)8 plane 12, there is a second AJGaAs layer with a wider forbidden band width than the first AJGaAs layer 16.
A type AjGaAs layer) 17 is formed.
上記した構成においては、ＧａＡｓ層１０の（００１）
面１１近傍領域は両側から禁制帯幅の広いｐ型ＡｊＧａ
Ａｓ層１７によって挾まれており、このため、ＧａＡｓ
層１０中にはｐ型ＡＮ ＧａＡｓ層１７に沿って空乏層
が形成される。In the above configuration, the (001) of the GaAs layer 10
The region near surface 11 is p-type AjGa with a wide forbidden band from both sides.
It is sandwiched between the As layers 17, and therefore the GaAs
A depletion layer is formed in layer 10 along p-type AN GaAs layer 17 .
空乏層に挾まれた電子！２０は極めて細い線状、即ち、
−次元の電子層となる。このような−次元電子層２０に
流れる電流は第２のＡｊＧａＡｓ層１７上に層圧７上加
することによって制御できる。Electrons trapped in the depletion layer! 20 is an extremely thin line, i.e.
It becomes a -dimensional electron layer. The current flowing through the -dimensional electron layer 20 can be controlled by applying a layer pressure of 7 on the second AjGaAs layer 17.
第２図は第１図に示された電子層２０中を流れる電流を
′Ｍ御する系を説明するための模式図である。第２図で
は、ＧａＡｓ層１０の下部に、ｐ型ＡＪ ＧａＡｓ層２
１か設けられている。図示されたＧａＡｓ層１０には、
３つの＜００１）面と、各（００１）面に隣接した（１
１１）Ｂ面が形成されており、各（００１）面及び（１
１１）Ｂ面は、第１及び第２のＡｊＧａＡｓ層１６及び
１７によって被覆されている。この構成では、容筒１の
Ａｌｌ ＧａＡｓ層１６下部のＧａＡｓ層１０中には、
電子層が第２図の前方から後方へ延びる方向に形成され
ている。また、第１のＡＪ ＧａＡｓ層１６の前方端及
び後方端は共通に接続されて、前方共通領域２２及び後
方共通領域２３を構成している。これら前方及び後方共
通領域２２及び２３はＧａＡｓ層１０の（００１）面上
に形成されているなめ、第１のＡＮ ＧａＡｓ層１６と
同様に、ｎ型ＡＪ ＧａＡｓ層であることは言うまでも
ない。FIG. 2 is a schematic diagram for explaining a system for controlling the current flowing through the electronic layer 20 shown in FIG. In FIG. 2, a p-type AJ GaAs layer 2 is formed below the GaAs layer 10.
1 is provided. The illustrated GaAs layer 10 includes:
Three <001) planes and (1
11) B plane is formed, each (001) plane and (1
11) The B side is covered with first and second AjGaAs layers 16 and 17. In this configuration, in the GaAs layer 10 below the All GaAs layer 16 of the container 1,
An electronic layer is formed in a direction extending from the front to the rear in FIG. Further, the front end and the rear end of the first AJ GaAs layer 16 are commonly connected to form a front common region 22 and a rear common region 23. Since these front and rear common regions 22 and 23 are formed on the (001) plane of the GaAs layer 10, it goes without saying that, like the first AN GaAs layer 16, they are n-type AJ GaAs layers.
前方及び後方共通領域２２及び２３上には、電子層の延
在方向を横切る方向に第１及び第２の電極２６及び２７
が設けられている。On the front and rear common areas 22 and 23, first and second electrodes 26 and 27 are arranged in a direction transverse to the direction in which the electronic layer extends.
is provided.
第２図では、第１及び第２の電極２６及び２７を用いて
、平行に延びる３本の電子層に一次元的に電流を流すこ
とができ、且つ、ｐ型
ＡｊＧａＡｓ層２１に印加される電圧を調節することに
よってＡｊＧａＡｓ層１７に印加される電圧を制御する
ことができる。これにより、電子層の二次元的な広がり
を調節することができ、したがって、電子層に流れる電
流の大きさを制御できる。In FIG. 2, by using the first and second electrodes 26 and 27, a current can be passed one-dimensionally through three electron layers extending in parallel, and a current can be applied to the p-type AjGaAs layer 21. By adjusting the voltage, the voltage applied to the AjGaAs layer 17 can be controlled. Thereby, the two-dimensional spread of the electronic layer can be adjusted, and therefore the magnitude of the current flowing through the electronic layer can be controlled.
（実施例２）
第３図は、本発明の池の実施例に係る化合物半導体装置
を示し、第１図と同一の機能を有する部分には同一の参
照符号が付されている。この化合物半導体装置を製作す
る場合、まず、下地のＧａＡｓ層１０に選択エツチング
を施して溝部を形成し、講部の底部に（００１）面１１
及び溝部の両側側面に（１１１）Ｂ面１２を露出させる
。(Embodiment 2) FIG. 3 shows a compound semiconductor device according to an embodiment of the present invention, and parts having the same functions as those in FIG. 1 are given the same reference numerals. When manufacturing this compound semiconductor device, first, the underlying GaAs layer 10 is selectively etched to form a groove, and the (001) plane 11 is formed at the bottom of the base.
The (111)B surface 12 is exposed on both side surfaces of the groove.
次に、露出された＜００１）面１１及び（１１１）８面
１２上に、ケイ素を不純物として
ＡＪＧａＡｓ層を成長させると、第１図の場合と同様に
、（００１）面１１上には、第１のＡＮ ＧａＡｓ層と
してｎ型Ａ、ＱＧａＡｓ層１６が形成されると共に、（
１１１）８面１２上には、第２のＡＮ ＧａＡｓ層とし
てｐ型Ａｊ ＧａＡｓ層１７が形成される。Next, when an AJGaAs layer is grown on the exposed <001) plane 11 and (111)8 plane 12 with silicon as an impurity, as in the case of FIG. 1, on the (001) plane 11, An n-type A, Q GaAs layer 16 is formed as the first AN GaAs layer, and (
111) A p-type Aj GaAs layer 17 is formed on the 8-plane 12 as a second AN GaAs layer.
第３図の実施例では、上記したｎ型及びｐ型ＡＮ Ｇａ
Ａｓ層１６及び１７の成長後、更に、高純度のＧａＡｓ
層３０を成長させる。この場合、高濃度の電子層２０′
が成長されたＧａＡｓ層３０内にも形成され、この電子
層２０′は第１図に示された実施例の場合と同様に禁制
帯幅の広いｐ型ＡＪ ＧａＡｓ層１７によって囲まれて
いるため、細い線状となる。In the embodiment shown in FIG. 3, the above n-type and p-type AN Ga
After growing the As layers 16 and 17, high purity GaAs is further grown.
Grow layer 30. In this case, the high concentration electron layer 20'
is also formed in the grown GaAs layer 30, and this electronic layer 20' is surrounded by the p-type AJ GaAs layer 17 with a wide forbidden band width, as in the embodiment shown in FIG. , becomes a thin line.
この構成において、電子層２０′中に流れる電流を制御
するためには、ＧａＡｓ層３０の電子層２０′に対応す
る位置にショットキー電極３１を設ければよい。In this configuration, in order to control the current flowing through the electronic layer 20', a Schottky electrode 31 may be provided at a position of the GaAs layer 30 corresponding to the electronic layer 20'.
上記した実施例では、ＧａＡｓ層の（００１）面と（１
１１）８面上にＡＮ ＧａＡｓ層を形成した場合につい
てのみ説明したが、本発明は何等これに限定されること
なく、池の■−Ｖ族化合物半導体（例えば、Ｉｎ、Ｐ等
を含む化合物半導体）を用いた場合、互いに異なる他の
方位面〈例えば、（００１）面と＜３１１）面）を用い
た場合、あるいは、Ｓｔ以外の不純物を用いた場合にも
同様に適用できる。In the above embodiment, the (001) plane and (1
11) Although only the case where an AN GaAs layer is formed on eight sides has been described, the present invention is not limited to this in any way, and can be applied to Ike's ■-V group compound semiconductor (for example, a compound semiconductor containing In, P, etc.). ), other different orientation planes (for example, (001) plane and <311) plane), or impurities other than St are similarly applicable.
（発明の効果）
以上述べたように、本発明によれば、−次元的に高密度
の電子層を形成することにより、このため、高速で且つ
駆動能力の大きな電界効果トランジス、夕を実現するこ
とができる。(Effects of the Invention) As described above, according to the present invention, by forming a dimensionally high-density electron layer, it is possible to realize a field effect transistor with high speed and large driving ability. be able to.
第１図は本発明の一実施例に係る化合物半導体装置を示
す図。第２図は第１図の化合物半導体装置を具体的に説
明するための斜視図。第３図は本発明の他の実施例に係
る化合物半導体装置の断面図。
１０・−ＧａＡｓ層、１６＝−ｎ−Ａｊ ＧａＡｓ、１
７−＝ｐ−ＡＮ ＧａＡｓ、２０．２０′−・・−次元
電子層、２６．２７・・・電極、３０−Ｇ ａ Ａ ｓ
層、３１・・・ショットキー電極。
第１図
第２図FIG. 1 is a diagram showing a compound semiconductor device according to an embodiment of the present invention. FIG. 2 is a perspective view for specifically explaining the compound semiconductor device of FIG. 1. FIG. 3 is a sectional view of a compound semiconductor device according to another embodiment of the present invention. 10·-GaAs layer, 16=-n-Aj GaAs, 1
7-=p-AN GaAs, 20.20'-...-dimensional electronic layer, 26.27... Electrode, 30-G a As
Layer 31... Schottky electrode. Figure 1 Figure 2
Claims (1)
異なる面方位を有し、前記第１の方位面と境界を接する
ように設けられた第２の方位面とを露出させたIII−Ｖ
族化合物半導体領域を備え、前記化合物半導体領域より
広い禁制帯幅を有する第１の化合物半導体結晶を前記第
１の方位面上に形成すると共に、前記第１の化合物半導
体結晶と同等以上の禁制帯幅を有する第２の化合物半導
体結晶を前記第２の方位面上に形成したことを特徴とす
る化合物半導体装置。 ２前記第１及び第２の方位面はそれぞれ （００１）及び（１１１）Ｂ方位面であることを特徴と
する特許請求の範囲第１項記載の化合物半導体装置。 ３前記第１及び第２の化合物半導体結晶中にIV族元素を
不純物として添加することを特徴とする特許請求の範囲
第１項記載の化合物半導体装置。 ４第１及び第２の化合物半導体に添加するIV族不純物元
素として、ケイ素（Ｓｉ）を用いることを特徴とする特
許請求の範囲第３項記載の化合物半導体装置。 ５前記第１の方位面上に、前記第１の化合物半導体結晶
を接合することによって第１の化合物半導体結晶中に形
成される電子層の両端に電極を設けると共に、前記第２
の化合物半導体結晶に電圧を印加することにより、前記
電子層中に流れる電流を制御することを特徴とする特許
請求の範囲第１項記載の化合物半導体装置。 ６予め定められた禁制帯幅を有する高純度層と該高純度
層より広い禁制帯幅を有し、且つ、前記高純度層より純
度の低い第１の化合物半導体層を接合した化合物半導体
装置において、前記高純度層は前記第１の化合物半導体
層との接合面と、当該接合面に隣接した側面とを有し、
前記側面には前記第１の化合物半導体層とは極性の異な
る第２の化合物半導体層が接合されていることを特徴と
する化合物半導体装置。[Claims] 1. A predetermined first azimuth plane and a second azimuth plane, which has a plane orientation different from the first azimuth plane and is provided so as to be in contact with the first azimuth plane. III-V with exposed azimuth plane
A first compound semiconductor crystal comprising a group compound semiconductor region and having a forbidden band width wider than the compound semiconductor region is formed on the first orientation plane, and a forbidden band width equal to or larger than that of the first compound semiconductor crystal. A compound semiconductor device, characterized in that a second compound semiconductor crystal having a width is formed on the second azimuth plane. 2. The compound semiconductor device according to claim 1, wherein the first and second azimuth planes are (001) and (111)B azimuth planes, respectively. 3. The compound semiconductor device according to claim 1, wherein a group IV element is added as an impurity into the first and second compound semiconductor crystals. 4. The compound semiconductor device according to claim 3, wherein silicon (Si) is used as the Group IV impurity element added to the first and second compound semiconductors. 5. Electrodes are provided on both ends of an electronic layer formed in the first compound semiconductor crystal by bonding the first compound semiconductor crystal on the first azimuth plane, and
2. The compound semiconductor device according to claim 1, wherein the current flowing through the electronic layer is controlled by applying a voltage to the compound semiconductor crystal. 6. In a compound semiconductor device in which a high-purity layer having a predetermined bandgap and a first compound semiconductor layer having a bandgap wider than the high-purity layer and having a lower purity than the high-purity layer are bonded. , the high purity layer has a bonding surface with the first compound semiconductor layer and a side surface adjacent to the bonding surface,
A compound semiconductor device, wherein a second compound semiconductor layer having a polarity different from that of the first compound semiconductor layer is bonded to the side surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149946A JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149946A JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH023250A true JPH023250A (en) | 1990-01-08 |
| JP2718511B2 JP2718511B2 (en) | 1998-02-25 |
Family
ID=15486035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63149946A Expired - Lifetime JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2718511B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011114160A (en) * | 2009-11-26 | 2011-06-09 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate |
| JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61210623A (en) * | 1985-03-15 | 1986-09-18 | Sony Corp | Manufacture of semiconductor device |
| JPS63299111A (en) * | 1987-05-29 | 1988-12-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of one-dimensional quantum thin line |
-
1988
- 1988-06-20 JP JP63149946A patent/JP2718511B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61210623A (en) * | 1985-03-15 | 1986-09-18 | Sony Corp | Manufacture of semiconductor device |
| JPS63299111A (en) * | 1987-05-29 | 1988-12-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of one-dimensional quantum thin line |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011114160A (en) * | 2009-11-26 | 2011-06-09 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate |
| JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2718511B2 (en) | 1998-02-25 |
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