JP2718511B2 - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JP2718511B2 JP2718511B2 JP63149946A JP14994688A JP2718511B2 JP 2718511 B2 JP2718511 B2 JP 2718511B2 JP 63149946 A JP63149946 A JP 63149946A JP 14994688 A JP14994688 A JP 14994688A JP 2718511 B2 JP2718511 B2 JP 2718511B2
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- layer
- semiconductor device
- plane
- algaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 45
- 150000001875 compounds Chemical class 0.000 title claims description 44
- 239000013078 crystal Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910021480 group 4 element Inorganic materials 0.000 claims 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 24
- 230000005669 field effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は極めて高速の移動度を有する電子を用いた化
合物半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a compound semiconductor device using electrons having extremely high mobility.
（従来の技術） 従来、この種の化合物半導体装置として、高純度層
と、該高純度層より広い禁制帯幅を有する電子供給層を
接合させた場合、高純度層内に二次元的に極めて移動度
の高い電子を含む電子層が生じることを利用した電界効
果型トランジスタが知られている。この電界効果型トラ
ンジスタでは、大きな移動度を持つ高濃度二次元電子に
よって高い相互コンダクタンスを実現できることが報告
されている。(Prior art) Conventionally, as a compound semiconductor device of this type, when a high-purity layer and an electron supply layer having a wider bandgap than the high-purity layer are bonded, two-dimensionally extremely 2. Description of the Related Art A field-effect transistor that utilizes an electron layer containing electrons having high mobility is known. It has been reported that in this field-effect transistor, high transconductance can be realized by high-concentration two-dimensional electrons having high mobility.
一方、電子を線状に、即ち、一次元的に閉じ込めるこ
とができれば、二次元的な電子層よりも、電子密度を高
くでき、相互コンダクタンスを更に高くできるものと考
えられる。しかしながら、従来の技術では、電子を一次
元的に閉じ込めることは非常に困難である。On the other hand, if electrons can be confined linearly, that is, one-dimensionally, it is considered that the electron density can be increased and the transconductance can be further increased as compared with the two-dimensional electron layer. However, it is very difficult to confine electrons one-dimensionally with the conventional technology.
（発明が解決しようとする課題） 本発明は、従来の化合物半導体装置に比べより高い相
互コンダクタンスを得ることができる化合物半導体装置
を提供することである。(Problem to be Solved by the Invention) An object of the present invention is to provide a compound semiconductor device capable of obtaining higher mutual conductance than a conventional compound semiconductor device.
本発明の他の目的は高濃度の電子を線状に閉じ込めて
一次元電子層を形成できる化合物半導体装置を提供する
ことを課題とする。Another object of the present invention is to provide a compound semiconductor device capable of forming a one-dimensional electron layer by confining a high concentration of electrons in a linear shape.
（課題を解決するため手段） 上記目的を達成するために、本発明に係る化合物半導
体装置は、面方位が（001）面である第１の面及び面方
位が（111）面であり、前記第１の面と境界を接するよ
うに設けられた第２の面を露出させたIII−Ｖ族化合物
半導体領域を備え、前記化合物半導体領域よりも広い禁
制帯幅を有する第１の化合物半導体結晶を前記第１の面
上に形成すると共に、前記第１の化合物半導体結晶より
も大きい禁制帯幅を有する第２の化合物半導体結晶を前
記第２の面上に形成したことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, in a compound semiconductor device according to the present invention, a first plane having a (001) plane and a (111) plane are provided. A first compound semiconductor crystal including a group III-V compound semiconductor region having a second surface exposed so as to be in contact with the first surface and having a wider bandgap than the compound semiconductor region; A second compound semiconductor crystal formed on the first surface and having a larger bandgap than the first compound semiconductor crystal is formed on the second surface.
（作用） 本発明によれば、第１の化合物半導体結晶から、高純
度層に流入した電子は、それをとり囲むように形成され
た（111）Ｂ面上の広い禁制帯幅を有する層によって両
側から閉じこめられて、実効的に細い線状の一次元電子
層となる。この一次元電子層を用いて相互コンダクタン
スの大きい電界効果型トランジスタを構成することがで
きる。(Function) According to the present invention, electrons flowing from the first compound semiconductor crystal into the high-purity layer are formed by the layer having a wide band gap on the (111) B plane formed so as to surround the high-purity layer. It is confined from both sides and effectively becomes a thin linear one-dimensional electron layer. Using this one-dimensional electron layer, a field effect transistor having a large transconductance can be formed.
以下、図面を参照して本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
（実施例１） 第１図を参照すると、本発明の一実施例に係る化合物
半導体装置は下地としてのGaAs層10を有し、このGaAs層
10は高純度層を形成している。GaAs層10の表面には、第
１の面方位する第１の面（以下、第１の方位面という）
として、（001）面11が線状に、即ち、一次元的に露出
されており、且つ、（001）面11の両側に、（001）面11
と境界を接するように設けられた第２の面方位を有する
第１の面（以下、第２の方位面という）としての（11
1）Ｂ面12が露出されている。ここで、GaAs層10はGaAs
基板であってもよく、また、エピタキシャル成長層であ
ってもよい。この関係で、GaAs層10はIII−Ｖ族化合物
半導体領域と呼ばれてもよい。上記した面方位が互いに
異なる第１および第２の方位面を露出させることはGaAs
層に通常の選択エッチングを施すことにより可能であ
る。Embodiment 1 Referring to FIG. 1, a compound semiconductor device according to an embodiment of the present invention has a GaAs layer 10 as a base, and this GaAs layer
10 forms a high-purity layer. On the surface of the GaAs layer 10, a first plane having a first plane orientation (hereinafter referred to as a first orientation plane) is provided.
The (001) plane 11 is linearly exposed, that is, one-dimensionally exposed, and the (001) plane 11 is provided on both sides of the (001) plane 11.
(11) as a first plane having a second plane orientation (hereinafter, referred to as a second orientation plane) provided so as to be in contact with the boundary.
1) The B side 12 is exposed. Here, the GaAs layer 10 is GaAs
It may be a substrate or an epitaxial growth layer. In this connection, the GaAs layer 10 may be called a III-V compound semiconductor region. Exposing the first and second orientation planes having different plane orientations from each other is performed by using GaAs.
This can be achieved by subjecting the layer to normal selective etching.
次に、（001）層11上に、電子供給層として第１のAlG
aAs層16を成長させると共に、（111）Ｂ面12上に第２の
AlGaAs層17を成長させる。ここで、第１及び第２のAlGa
As層16及び17には、不純物としてケイ素（Si）が添加さ
れており、これらAlGaAs層16及び17はGaAs層10より広い
禁制帯を有している。Next, on the (001) layer 11, the first AlG
While growing the aAs layer 16, a second
An AlGaAs layer 17 is grown. Here, the first and second AlGa
Silicon (Si) is added as an impurity to the As layers 16 and 17, and the AlGaAs layers 16 and 17 have a wider forbidden band than the GaAs layer 10.
通常、（001）面11上のIII−Ｖ族化合物半導体に添加
したケイ素はドナーとなり、ｎ型ドーパントとして働く
が、（111）Ｂ面12上のIII−Ｖ族化合物半導体に添加し
た場合、アクセプタとなり、ｐ型ドーパントとして働く
ことが知られている。Normally, silicon added to the group III-V compound semiconductor on the (001) plane 11 serves as a donor and acts as an n-type dopant, but when added to the group III-V compound semiconductor on the (111) B plane 12, the acceptor Which is known to work as a p-type dopant.
また、高温でAlGaAs層を形成する場合、同一成長条件
下であっても、（111）Ｂ面12では（001）面11に比べ
て、Ga原子の脱離量が多く、結果として、（111）Ｂ面1
2には、（001）面11よりもAl組成の高いAlGaAs層が形成
されることが判明した。このことは、同一条件で生成さ
れた第１及び第２のAlGaAs層16及び17のうち、（111）
Ｂ面12上に形成された第２のAlGaAs層17は（001）面11
上に形成された第１のAlGaAs層16に比べて広い禁制帯幅
を有していることになる。Also, when forming an AlGaAs layer at a high temperature, even under the same growth conditions, a larger amount of Ga atoms is desorbed in the (111) B plane 12 than in the (001) plane 11, and as a result, (111) ) B side 1
It was found that an AlGaAs layer having a higher Al composition than the (001) plane 11 was formed in No. 2. This means that, of the first and second AlGaAs layers 16 and 17 generated under the same conditions, (111)
The second AlGaAs layer 17 formed on the B surface 12 has a (001) surface 11
It has a wider bandgap than the first AlGaAs layer 16 formed thereon.
以上述べた構成では、（001）面11上には、GaAs層10
より広い禁制帯幅を有する第１のAlGaAs層（ｎ型AlGaAs
層）16が形成され、GaAs層10とヘテロ接合をなし、GaAs
層10中に電子ガス層（以下、単に、電子層と呼ぶ）20を
生成する。また、（111）Ｂ面12上には、第１のAlGaAs
層16より更に禁制帯幅の広い第２のAlGaAs層（ｐ型AlGa
As層）17が形成されている。In the configuration described above, the GaAs layer 10
First AlGaAs layer having a wider band gap (n-type AlGaAs
Layer 16 is formed and forms a heterojunction with the GaAs layer 10;
An electron gas layer (hereinafter, simply referred to as an electronic layer) 20 is generated in the layer 10. On the (111) B plane 12, a first AlGaAs
A second AlGaAs layer having a wider band gap than the layer 16 (p-type AlGa
As layer) 17 is formed.
上記した構成においては、GaAs層10の（001）面11近
傍領域では両側から禁制帯幅の広いｐ型AlGaAs層17によ
って挾まれており、このため、GaAs層10中にはｐ型AlGa
As層17に沿って空乏層が形成される。空乏層に挾まれた
電子層20は極めて細い線状、即ち、一次元の電子層とな
る。このような一次元電子層20に流れる電流は第２のAl
GaAs層17上に電圧を印加することによって制御できる。In the above-described structure, the GaAs layer 10 is sandwiched by the p-type AlGaAs layer 17 having a wide bandgap from both sides in the vicinity of the (001) plane 11 of the GaAs layer 10.
A depletion layer is formed along the As layer 17. The electron layer 20 sandwiched between the depletion layers becomes an extremely thin line, that is, a one-dimensional electron layer. The current flowing through the one-dimensional electron layer 20 is the second Al
It can be controlled by applying a voltage on the GaAs layer 17.
第２図は第１図に示された電子層20中を流れる電流を
制御する系を説明するための模式図である。第２図で
は、GaAs層10の下部に、ｐ型AlGaAs層21が設けられてい
る。図示されたGaAs層10には、３つの（001）面と、各
（001）面に隣接した（111）Ｂ面が形成されており、各
（001）面及び（111）Ｂ面は、第１及び第２のAlGaAs層
16及び17によって被覆されている。この構成では、各第
１のAlGaAs層16下部のGaAs層10中には、電子層が第２図
の前方から後方へ延びる方向に形成されている。また、
第１のAlGaAs層16の前方端及び後方端は共通に接続され
て、前記共通領域22及び後方共通領域23を構成してい
る。これら前方及び後方共通領域22及び23はGaAs層10の
（001）面上に形成されているため、第１のAlGaAs層16
と同様に、ｎ型AlGaAs層であることは言うまでもない。FIG. 2 is a schematic diagram for explaining a system for controlling the current flowing in the electronic layer 20 shown in FIG. In FIG. 2, a p-type AlGaAs layer 21 is provided below the GaAs layer 10. The illustrated GaAs layer 10 has three (001) planes and a (111) B plane adjacent to each (001) plane, and each (001) plane and (111) B plane are First and second AlGaAs layers
Coated with 16 and 17. In this configuration, an electron layer is formed in the GaAs layer 10 below each first AlGaAs layer 16 in a direction extending from the front to the rear in FIG. Also,
The front end and the rear end of the first AlGaAs layer 16 are commonly connected to form the common region 22 and the rear common region 23. Since these front and rear common regions 22 and 23 are formed on the (001) plane of the GaAs layer 10, the first AlGaAs layer 16
Needless to say, it is an n-type AlGaAs layer as in the case of the above.
前方及び後方共通領域22及び23上には、電子層の延在
方向を横切る方向に第１及び第２の電極26及び27が設け
られている。On the front and rear common regions 22 and 23, first and second electrodes 26 and 27 are provided in a direction crossing the extending direction of the electronic layer.
第２図では、第１及び第２の電極26及び27を用いて、
平行に延びる３本の電子層に一次元的に電流を流すこと
ができ、且つ、ｐ型AlGaAs層21に印加される電圧を調節
することによってAlGaAs層17に印加される電圧を制御す
ることができる。これにより、電子層の二次元的な広が
りを調節することができ、したがって、電子層に流れる
電流の大きさを制御できる。In FIG. 2, using the first and second electrodes 26 and 27,
A current can flow one-dimensionally through the three electron layers extending in parallel, and the voltage applied to the AlGaAs layer 17 can be controlled by adjusting the voltage applied to the p-type AlGaAs layer 21. it can. Thereby, the two-dimensional spread of the electronic layer can be adjusted, and therefore, the magnitude of the current flowing through the electronic layer can be controlled.
（実施例２） 第３図は、本発明の他の実施例に係る化合物半導体装
置を示し、第１図と同一の機能を有する部分には同一の
参照符号が付されている。この化合物半導体装置を製作
する場合、まず、下地のGaAs層10に選択エッチングを施
して溝部を形成し、溝部の底部に（001）面11及び溝部
の両側側面に（111）Ｂ面12を露出させる。次に、露出
させた（001）面11及び（111）Ｂ面12上に、ケイ素を不
純物としてAlGaAs層を成長させると、第１図の場合と同
様に、（001）面11上には、第１のAlGaAs層としてｎ型A
lGaAs層16が形成されると共に、（111）Ｂ面12上には、
第２のAlGaAs層としてｐ型AlGaAs層17が形成される。Embodiment 2 FIG. 3 shows a compound semiconductor device according to another embodiment of the present invention, and portions having the same functions as those in FIG. 1 are denoted by the same reference numerals. When manufacturing this compound semiconductor device, first, a groove is formed by selectively etching the underlying GaAs layer 10, and the (001) plane 11 is exposed at the bottom of the groove and the (111) B plane 12 is exposed on both side surfaces of the groove. Let it. Next, when an AlGaAs layer is grown using silicon as an impurity on the exposed (001) plane 11 and (111) B plane 12, as in the case of FIG. N-type A as the first AlGaAs layer
The lGaAs layer 16 is formed, and on the (111) B plane 12,
A p-type AlGaAs layer 17 is formed as a second AlGaAs layer.
第３図の実施例では、上記したｎ型及びｐ型AlGaAs層
16及び17の成長後、更に、高純度のGaAs層30を成長させ
る。この場合、高純度の電子層20′が成長させたGaAs層
30内にも形成され、この電子層20′は第１図に示された
実施例の場合と同様に禁制帯幅の広いｐ型AlGaAs層17に
よって囲まれているため、細い線状となる。In the embodiment of FIG. 3, the n-type and p-type AlGaAs layers described above are used.
After the growth of 16 and 17, a high-purity GaAs layer 30 is further grown. In this case, the GaAs layer on which the high-purity electron layer 20 'was grown
The electron layer 20 'is formed in the p-type AlGaAs layer 17 having a wide band gap as in the embodiment shown in FIG.
この構成において、電子層20′中に流れる電流を制御
するためには、GaAs層30の電子層20′に対応する位置に
ショットキー電極31を設ければよい。In this configuration, in order to control the current flowing through the electronic layer 20 ', the Schottky electrode 31 may be provided at a position of the GaAs layer 30 corresponding to the electronic layer 20'.
上記した実施例では、GaAs層の（001）面と（111）Ｂ
面上にAlGaAs層を形成した場合についてのみ説明した
が、本発明は何等これに限定されることなく、他のIII
−Ｖ族化合物半導体（例えば、In,P等を含む化合物半導
体）を用いた場合、互いに異なる他の方位面（例えば、
（001）面と（311）面）を用いた場合、あるいは、Si以
外の不純物を用いた場合にも同様に適用できる。In the above embodiment, the (001) plane of the GaAs layer and the (111) B
Although only the case where the AlGaAs layer is formed on the surface has been described, the present invention is not limited to this, and other III
In the case of using a group V compound semiconductor (for example, a compound semiconductor containing In, P, etc.), other orientation planes different from each other (for example,
The same applies to the case of using the (001) plane and the (311) plane) or the case of using impurities other than Si.
（発明の効果） 以上述べたように、本発明によれば、一次元的に高密
度の電子層を形成することにより、このため、高速で且
つ駆動能力の大きな電界効果トランジスタを実現するこ
とができる。(Effects of the Invention) As described above, according to the present invention, by forming a one-dimensionally high-density electron layer, a high-speed field-effect transistor having a large driving capability can be realized. it can.
第１図は本発明の一実施例に係る化合物半導体装置を示
す図。第２図は第１図の化合物半導体装置を具体的に説
明するための斜視図。第３図は本発明の他の実施例に係
る化合物半導体装置の断面図。 10…GaAs層、16…ｎ−AlGaAs、17…ｐ−AlGaAs、20,2
0′…一次元電子層、26,27…電極、30…GaAs層、31…シ
ョットキー電極。FIG. 1 is a diagram showing a compound semiconductor device according to one embodiment of the present invention. FIG. 2 is a perspective view for specifically explaining the compound semiconductor device of FIG. FIG. 3 is a sectional view of a compound semiconductor device according to another embodiment of the present invention. 10 ... GaAs layer, 16 ... n-AlGaAs, 17 ... p-AlGaAs, 20,2
0 ': One-dimensional electron layer, 26, 27 ... electrodes, 30: GaAs layer, 31: Schottky electrode.
Claims (5)
方位が（111）面であり、前記第１の面と境界を接する
ように設けられた第２の面を露出させたIII−Ｖ族化合
物半導体領域を備え、前記化合物半導体領域よりも広い
禁制帯幅を有する第１の化合物半導体結晶を前記第１の
面上に形成すると共に、前記第１の化合物半導体結晶よ
りも大きい禁制帯幅を有する第２の化合物半導体結晶を
前記第２の面上に形成したことを特徴とする化合物半導
体装置。A first surface having a plane orientation of (001) and a second surface having a plane orientation of (111) which is provided so as to be in contact with the first surface; Forming a first compound semiconductor crystal having a bandgap wider than the compound semiconductor region on the first surface, wherein the first compound semiconductor crystal has a wider bandgap than the compound semiconductor region. A compound semiconductor device, wherein a second compound semiconductor crystal having a large forbidden band width is formed on the second surface.
IV族元素を不純物として添加することを特徴とする特許
請求の範囲第１項記載の化合物半導体装置。2. The semiconductor device according to claim 1, wherein said first and second compound semiconductor crystals include:
2. The compound semiconductor device according to claim 1, wherein a group IV element is added as an impurity.
族不純物元素として、ケイ素（Si）を用いることを特徴
とする特許請求の範囲第２項記載の化合物半導体装置。3. IV added to the first and second compound semiconductors.
3. The compound semiconductor device according to claim 2, wherein silicon (Si) is used as the group III impurity element.
体結晶を接合することによって第１の化合物半導体結晶
中に形成される電子層の両端に電極を設けると共に、前
記第２の化合物半導体結晶に電圧を印加することによ
り、前記電子層中に流れる電流を制御することを特徴と
する特許請求の範囲第１項記載の化合物半導体装置。4. An electrode is provided at both ends of an electron layer formed in the first compound semiconductor crystal by joining the first compound semiconductor crystal on the first surface, and 2. The compound semiconductor device according to claim 1, wherein a current flowing in said electronic layer is controlled by applying a voltage to said compound semiconductor crystal.
と該高純度層より広い禁制帯幅を有し、且つ、前記高純
度層より純度の低い第１の化合物半導体層を結合した化
合物半導体装置において、前記高純度層は前記第１の化
合物半導体層との接合面と、当該接合面に隣接した側面
とを有し、前記側面には前記第１の化合物半導体層とは
極性の異なる第２の化合物半導体層が接合されているこ
とを特徴とする化合物半導体装置。5. A high purity layer having a predetermined band gap and a first compound semiconductor layer having a wider band gap than the high purity layer and having a lower purity than the high purity layer. In the compound semiconductor device, the high-purity layer has a bonding surface with the first compound semiconductor layer and a side surface adjacent to the bonding surface, and the side surface has a polarity opposite to that of the first compound semiconductor layer. A compound semiconductor device, wherein different second compound semiconductor layers are joined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149946A JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149946A JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH023250A JPH023250A (en) | 1990-01-08 |
| JP2718511B2 true JP2718511B2 (en) | 1998-02-25 |
Family
ID=15486035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63149946A Expired - Lifetime JP2718511B2 (en) | 1988-06-20 | 1988-06-20 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2718511B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011114160A (en) * | 2009-11-26 | 2011-06-09 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device and method of manufacturing the semiconductor substrate |
| JP5667360B2 (en) * | 2009-12-21 | 2015-02-12 | 住友化学株式会社 | Semiconductor substrate, electronic device, and method for manufacturing semiconductor substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0620039B2 (en) * | 1985-03-15 | 1994-03-16 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JP2533777B2 (en) * | 1987-05-29 | 1996-09-11 | 日本電信電話株式会社 | Method for manufacturing one-dimensional quantum wire |
-
1988
- 1988-06-20 JP JP63149946A patent/JP2718511B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH023250A (en) | 1990-01-08 |
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