JPH0232449A - Register designating system - Google Patents

Abstract

PURPOSE:To easily alter an address to be designated by providing a base register inside a circumferential chip, and designating an internal register by means of the internal address generated from a value stored into the base register and a value inputted from a processor. CONSTITUTION:A processor 1 outputs a value 1024 onto an address bus 4, outputs a value 3072 onto a data bus 6, and outputs writing onto a signal line 101. For the value 1024, a circumferential chip 2 inputs the types of access on the signal line 101 through a signal line 202, subtracts the value 1024 of a base register 20 inputted from the value 1024 through a signal line 203 by a subtracter 24, and according to the types of the access inputted through the signal line 202, the value 3072 on the data bus 6 through a signal line 205 to an internal register 21, in which an internal address is set at a value zero. Thus, the address to be designated can be easily altered.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a register specification method, and more specifically, in an information processing device composed of a processor and a plurality of peripheral chips, the present invention relates to a register specification method, and more specifically, in an information processing device consisting of a processor and a plurality of peripheral chips, a Concerning register specification method when performing access.

[Conventional technology]

In an information processing device consisting of a processor and multiple peripheral chips, in order for the processor to access the internal registers of the peripheral chips, the internal registers of each peripheral chip must be uniquely specified by the address output from the processor. be.

FIG. 2 is a block diagram illustrating the conventional register specification method, in which 1 is a processor, 2 and 3 are peripheral chips, 4 is an upper address bus, 5 is a lower address bus, 6 is a data bus, 7 is a decoder, 21 22.23 is an internal register of the peripheral chip 2, and 31.degree. 32.33 is an internal register of the peripheral chip 3.

In this case, it is assumed that the upper address bus 4 has a width of 6 bits, the lower address bus 5 has a width of 10 bits, and the address is specified by a 16-bit pure binary number obtained by combining the southern address buses 4 and 5. However, the following explanation uses values obtained by converting pure binary numbers to decimal numbers.

In FIG. 2, internal register 21.2 of peripheral chip 2
2.23 are the addresses "1025J, r10" respectively.
26J, specified by r1027J, peripheral chip 3
Registers 31, 32, and 33 are at L/X, respectively.
r2049J, r2050J.

Suppose that it is specified by r2051J. The decoder 7 is
The value on the upper address bus 4 is rlJ (000001
), access from processor 1 to peripheral chip 2 is enabled, and the value on upper address bus 4 is Il.
” (OOo O10), the internal registers 21, 22, and 23 of the peripheral chip 2, which enable access from the processor 1 to the peripheral chip 3, set the values of the lower address bus 5 to “1” (Oooooooool), respectively. "
2” (0000000010), r3J (00000
00011), and the internal registers 31, 32, and 33 of the 1st peripheral chip 3 are also each "1".

Specified by "2" and "3".

For example, from the processor 1 to the internal register 2 of the peripheral chip 2
2 is accessed as follows.

The processor 1 outputs "1" on the upper address bus 4 and "2" on the lower address bus 5 (i.e., the address r1026J (000001000000001
0)) and outputs the type of access (read or write) on the signal line 101. The decoder 7 inputs the value on the upper address bus 4 via the signal line 701, and since the input value is "1" (000001), the decoder 7 sends the internal register from the processor 1 to the peripheral chip 2 via the signal line 702. The peripheral chip 2 notifies the processor 1 via the signal line 702 that an access request to the internal register has occurred, and outputs the signal onto the lower address bus 5. The value “2”
” is input via the signal line 201, and the type of access output on the signal line 101 is input via the signal line 202.

The peripheral chip 2 receives the value input via the signal line 201.
0 peripheral that inputs and outputs data between the data bus 6 and the internal register 22 via the signal line 203 according to the type of access input via the signal line 202 to the register 22 whose internal address is ``2''. On chip 3, signal line 7
03, it learns that the access request from processor 1 is not for its own chip, and ignores the access.

[Problem to be solved by the invention]

As mentioned above, in the conventional register specification method, by decoding a part of the address output from the processor, the peripheral chip that has the internal register to be accessed by the processor is selected, and the remaining accesses from the processor are transferred to one chip. Access to internal registers was performed by making it valid only for peripheral chips. but,
This method requires a decoder, but it also has the disadvantage that the decoder must be changed if the number or type of peripheral chips used or the addresses that designate internal registers are changed.

The purpose of the present invention is to eliminate the need for a decoder, and also to make it possible to specify an internal register with an arbitrary address.
It is an object of the present invention to provide a register designation method that can easily change an address designating an internal register.

[Means to solve the problem]

In order to achieve the above object, in the register specification method of the present invention, each peripheral chip is provided with a base register that can be accessed from the processor in the same way as the internal register. This is characterized in that an internal address is generated by calculating the value stored in the internal register, and an internal register is specified by the generated internal address.

[Operation] When accessing from the processor, the peripheral chip specifies the internal register to be accessed using an internal address generated from the value stored in the base register and the value output from the processor, eliminating the need for a decoder. becomes. In addition, since the base register can be accessed from the processor in the same way as the internal registers, by changing the value of the base register with a write operation from the processor, the internal register can be specified with an arbitrary address. Addresses specifying internal registers can be easily changed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which 1 is a processor, 2 and 3 are peripheral chips, 4 is an address bus, and 6 is a block diagram of an embodiment of the present invention.
1 is a data bus, and 101 is a control signal line. Peripheral chip 2 has base register 20, internal registers 21, 22, 2
3. Consists of a subtractor 24. Similarly, the peripheral chip 3 also includes a base register 3o, internal registers 31, 32, 33, and a subtracter 34. It is assumed that the address bus 4 has a width of 16 bits and is designated by a 16-bit pure binary number. Tazoshi,
In the following explanation, values obtained by converting pure binary numbers into decimal numbers will be used as in the case of FIG. 2.

In FIG. 1, the base register 20 of the peripheral chip 2,
Internal registers 21, 22, and 23 each have address r1024J of address bus 4.

The base register 30 and internal registers 31, 32.33 of one peripheral chip 3 specified by r1025J, r1026J, and r1027J are addresses r2048J and r2049J of the address bus 4, respectively.

It is specified by "205o" and "2o51".

Also, a base register 20, internal registers 21, 22.
Each of the 23 internal addresses is "0".

rlJ, r2J, r3J, and base register 3
o, and the internal addresses of internal registers 31, 32, and 33 are also rOJ, rlJ, r2J, and r3J, respectively. The base registers 20 and 30 each have a value r1024 corresponding to their own address.

Assume that r2048J is set.

For example, from the processor 1 to the internal register 2 of the peripheral chip 2
2 is accessed as follows.

Processor 1 writes “1026” (0) on address bus 4.
000010000000010), and signal line 1
The type of access (read or write) is output on 01.The peripheral chip 2 inputs the value rlO26J output on the address bus 4 via the signal line 201,
The type of access output on the signal line 101 is input via the signal 202. The subtracter 24 is connected to the signal line 201
The value r1024 of the base register 20 inputted via the signal line 203 from the value rl026J inputted via the
0000010000000000) and outputs the value “2” to the signal line 204. The peripheral chip 2 accesses the data bus 6 via the signal line 205 according to the type of access input via the signal line 202 to the register 22 whose internal address is the value "2" output on the signal line 204. Data is input/output between the internal register 22 and the internal register 22.

On the other hand, the peripheral chip 3 inputs the value rlO26J output on the address bus 4 via the signal line 301,
The type of access output on the signal line 101 is input via the signal line 302.

The subtracter 34 receives the value rl input via the signal line 301.
The value r20484 of the base register 20 input from O26J via the signal line 203 (0000100000
000000) and sends the value r-1022 to the signal line 204.
Output J. As a result, the peripheral chip 3
Since there is no register whose internal address is the value output on 04, it is assumed that the access request from processor 1 is not for its own chip, and the access is ignored.

Next, the operation of changing the value of the base register 20 of the peripheral chip 2o to, for example, r3072J will be described.

The processor 1 outputs "1024" on the address bus 4, outputs "r3072" on the data bus 6, and outputs write as the type of access on the signal line 101. The peripheral chip 2 receives the value r output on the address bus 4.
1024J is input through the signal line 201, and the signal line 10
The type of access output on 1 is input via signal line 202. The subtracter 24 subtracts the value "r1024" of the base register 20 input via the signal line 203 from the value "1024" input via the signal line 201, and outputs the value "0" to the signal line 204. 2 is a data bus input via the signal line 205 according to the type of access input via the signal line 202 to the base register 20 whose internal address is the value "0" output on the signal line 204. Write the value r3072J on 6.

On the other hand, the peripheral chip 3 inputs the value r1024J output on the address bus 4 via the signal m301, and inputs the type of access output on the signal 101 to the signal line 3.
Input via 02. The subtracter 34 subtracts the value r2048J of the base register 2o input via the signal line 203 from "1024" input via the signal line 301,
The value r-1024J is output to the signal line 204. As a result.

This is because the peripheral chip 3 does not have a register that uses the value output on the signal line 204 as an internal address.

It is assumed that the access request from processor 1 is not for its own chip, and the access is ignored.

With the above operation, it becomes possible to specify an internal register by subtracting the value of the base register from the address output by the processor. It becomes possible to change the address.

〔Effect of the invention〕

As explained above, according to the present invention, a base register is provided inside a peripheral chip, and an internal register to be accessed is determined by an internal address generated from a value stored in the base register and a value input from a processor. By specifying this, there is no need for a decoder to specify the peripheral chip that has the internal register that the processor accesses.Also, if you change the number or type of peripheral chips used and change the address that specifies the internal register. , by changing the value of the base register.

Addresses specifying internal registers can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the register designation method of the present invention, and FIG. 2 is a block diagram of a conventional register designation method. 1... Processor, 2, 3... Peripheral chip, 4.
...address bus, 6...data bus. 20... Base register, 21.22, 23... Internal register, 24... Subtractor, 30... Base register, 31.32, 33.
...Internal register, 34...Subtractor.

Claims (1)

[Claims] (1) Consists of a processor and multiple peripheral chips,
In an information processing device in which each peripheral chip has a plurality of internal registers that are accessed by the processor, each peripheral chip has a base register that can be accessed from the processor in the same way as the internal registers described above, and when accessed by the processor, the processor outputs A register specification method characterized in that an internal address is generated by calculating the address and a value stored in the base register, and an internal register or a base register is specified by the generated internal address.