JPH0231240A - Processing system for troubled coprocessor - Google Patents

Abstract

PURPOSE:To ensure the continuous operation of a system with no interruption for a data processor by simulating a faulty coprocessor with an EPU instruction in case the trouble of the coprocessor is detected by a patrol test during operation of the system. CONSTITUTION:A CPU 2 fetches an instruction out of a main memory 3 via an instruction fetching means 21 and decides whether this instruction is given from an EPU or a coprocessor via an instruction deciding means 22. If an instruction of the coprocessor is decided, a coprocessor instruction execution stop deciding means 13 decides whether said instruction is set under an execution permission state or a stop state. Then an operating system exception processing part 5 is started by an exception generating means 24 and decides the presence or absence of the trouble of the coprocessor via a coprocessor trouble information retrieving means 31.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for handling a failure that occurs during system operation in a data processing device, and particularly to a method for handling a failure of a coprocessor.

[Conventional technology]

Conventionally, the method for handling failures that occur during system operation of data processing equipment is system down.

Alternatively, the faulty equipment was to be disconnected.

[Problem to be solved by the invention]

In the above-described conventional failure handling method, the system is brought down unconditionally or the failed device is disconnected, so the job being executed must be forcibly terminated, which has the disadvantage of having a negative impact on system users.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processing method in the event of a coprocessor failure, which improves the above-mentioned drawbacks by simulating coprocessor instructions with EPU instructions.

[Means to solve the problem]

The coprocessor failure processing method according to the present invention includes a coprocessor instruction execution inhibiting means that sets a coprocessor instruction to an execution inhibited state when a coprocessor failure is detected through a patrol test that periodically tests the functions of a data processing device. a coprocessor failure information registration means that registers a failure of the coprocessor as information in conjunction with the coprocessor instruction execution inhibiting means; an instruction determination means that determines whether an executed instruction is an EPU instruction or a coprocessor instruction; Coprocessor instruction execution inhibition determining means determines whether the coprocessor instruction execution is inhibited when the instruction is determined to be a coprocessor instruction by the instruction determining means; an exception generating means for generating an exception when an exception occurs due to the execution of a coprocessor instruction; a coprocessor failure information search means for searching for the presence or absence of a coprocessor failure from the coprocessor failure information; and the coprocessor failure information and coprocessor instruction simulating means for simulating the coprocessor instruction using an EPU instruction when it is determined by the search means that there is a failure in the coprocessor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, the processing method when a coprocessor fails is data processing device 1. The data processing device 1 includes a central processing unit 2 and a main memory 3, and the main memory 3 includes a patrol test section 4 and an operating system exception handling section 5.

FIG. 2 is a flowchart showing the processing of the patrol test section 4. In the figure, the patrol test section 4 includes a functional test execution means 11. Coprocessor failure determination means 12. Coprocessor instruction execution inhibiting means 13. It consists of coprocessor failure information registration means 14.

FIG. 3 is a flowchart showing the processing of the central processing unit 2. In the figure, the central processing unit 2 includes instruction fetch means 21.
Command determining means 22. It is composed of a coprocessor instruction execution inhibition determination means 231, an exception generation means 24, and an instruction execution means 25.

FIG. 4 is a flowchart showing the processing of the operating system exception handling section 5. In the figure, the operating system exception handling unit 5 includes a coprocessor failure information retrieval unit 31. It consists of a coprocessor instruction simulator 5 means 321 and a normal exception handling means 33.

First, in the patrol test section 4, the functional test execution means 11 executes a functional test of the data processing apparatus, and the coprocessor failure determination means 12 determines whether or not there is a failure in the coprocessor. If it is determined that there is a failure in the coprocessor, the coprocessor instruction execution inhibiting means 13 sets the execution of the coprocessor instruction to a inhibited state, and the coprocessor failure information registration means 1
At step 4, failure information of the coprocessor is registered and the process ends.

Next, after the central processing unit 2 fetches an instruction from the main memory by the instruction fetching means 21, the instruction determining means 22 determines whether this instruction is an EPU instruction or a coprocessor instruction.
Determine by. If the instruction is determined to be a coprocessor instruction, the coprocessor instruction execution inhibition determining means 13 determines whether the coprocessor instruction is in an execution permitted state or in an execution inhibited state. Furthermore, if it is determined that the execution is inhibited, the exception generating means 24 generates an exception, and the process returns to the beginning again.

Next, the operating system exception handling section 5 is activated by the exception generation means 24, and the coprocessor failure information retrieval means 31 determines whether there is a failure in the coprocessor. If it is determined that there is a failure in the coprocessor, the coprocessor instruction simulator 32 sends the coprocessor instruction to the EPU.
Simulate with the command and end the process.

〔Effect of the invention〕

As explained above, the present invention enables operation without stopping the system by simulating the failed coprocessor using EPU instructions when a failure of a coprocessor is detected by a patrol test during system operation in a data processing device. It has a long-lasting effect.

processor failure information registration means, 22...command discrimination means, 2
3... Coprocessor instruction execution inhibition determining means, 24...
・Exception generation means, 31...Coprocessor failure information search means, 32...Coprocessor instruction simulation means.

Claims (1)

[Claims] coprocessor instruction execution inhibiting means for setting a coprocessor instruction to an execution inhibiting state when a failure of the coprocessor is detected through a patrol test that periodically tests the functions of the data processing device, and interlocking with the coprocessor instruction execution inhibiting means. coprocessor failure information registration means for registering a failure of the coprocessor as information; instruction determination means for determining whether an executed instruction is an EPU instruction or a coprocessor instruction; and when the instruction determination means determines that the execution instruction is a coprocessor instruction. coprocessor instruction execution inhibition determining means for determining whether the coprocessor instruction execution is inhibited; an exception generating means for generating an exception when the coprocessor instruction execution inhibition determining means determines that the coprocessor instruction execution is inhibited; coprocessor failure information search means for searching for the presence or absence of a coprocessor failure based on the coprocessor failure information when an exception occurs due to execution of an instruction; and when it is determined by the coprocessor failure information search means that there is a failure of the coprocessor. A method for processing when a coprocessor fails, comprising: coprocessor instruction simulating means for simulating the coprocessor instruction using an EPU instruction.