JPH07105045A - Debugging system for information processor function test program - Google Patents

Abstract

PURPOSE:To eliminate countermeasure by a manual operation and to highly efficiently execute debugging by debugging a function test program through the use of an information processor different from the information processor of a test object. CONSTITUTION:The operation fo the information processor consisting of an instruction processor 23, a main storage device 21 and an input/output device 27 is verified by loading the function test program on the main storage device and making the instruction processor 23 to execute it. The function test program is debugged by using the information processor different from the information processor which the function test program sets to be the test object. Abnormal termination interruption is adopted and an instruction having become abnormal termination and an operation on the architecture of the input/output device 27 are simulated on abnormal termination owing to the issuing of a generated non-support instruction and the designation of the input/output device. Furthermore, a means for automatically re-executing the operation from an interruption- occurred place is provided so as to execute the function test program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to debugging of a function test program for verifying the function of an information processing device, and solves a problem that occurs when an information processing device different from the information processing device to be tested is used. , A debugging method by means of eliminating the need for manual intervention.

[0002]

2. Description of the Related Art In developing a new technology, a new function and a new architecture for an information processing apparatus, it is indispensable to have high performance and high quality.

Therefore, a function test program is developed as a means for verifying these at the same time as hardware design, and is used as a guarantee of quality by judging the normality of each device.

Therefore, the function test program itself is required to be of high quality with no defects so as not to affect not only the verification accuracy but also the development schedule of the hardware. However, due to the fact that the environment itself for executing the function test program is under development and the scale and function of the function test program are increasing with the sophistication of the information processing equipment, it is very difficult. It's coming. In order to deal with such a problem, there is a technique described in Japanese Patent Laid-Open No. 03-102540. That is, an architectural environment equivalent to the information processing device to be tested is virtually constructed by software operable under the OS of another information processing device, and a series of processing of the function test program can be executed. The quality is ensured by developing an instruction simulator and using it for debugging.

However, since the instruction simulator operates under the OS, it has a large difference in main memory capacity, processing performance, etc. compared to the actual machine, and each processor in a system having a plurality of instruction processors. It is difficult to create an environment where asynchronous operations and asynchronous operations of I / O devices occur, and even if the environment operates normally under the instruction simulator, if you execute it on the actual machine, it will be different depending on the environment. Defects may occur, and there is a high possibility that wasteful man-hours for these analyzes will be required during the verification period of the information processing device to be tested.

Therefore, at the final stage of the debug period,
It is necessary to take measures to improve the quality of the functional test program by performing actual machine debugging directly under the information processing device having a function or architecture similar to that of the information processing device to be tested.

[0007]

The problem to be solved is that the information processing device used at the final stage of the debug period is usually a conventional model different from the information processing device to be tested, or Since the test target information processing device in which the functions of the parts are enabled is used, in the function test program, since unsupported instructions and input / output devices are often used in these information processing devices, abnormal operation frequently occurs. However, each time, the number of man-hours required for the analysis of the cause and the work of a program patch for avoiding the problem becomes extremely large.

The object of the present invention is to solve these problems of the prior art, to solve the problems caused by debugging of the functional test program, and to eliminate the need for manual intervention, thereby enabling highly efficient debugging. It provides a debugging method that

[0009]

In order to achieve the above object, the debugging method of the present invention comprises (1) an instruction processor and a group of peripheral devices such as a main memory and an input / output device connected to the processor. In the function test method for verifying the operation of the information processing device by loading the function test program into the main storage device and causing the instruction processor to execute the function test program, If the instruction is an unsupported instruction of the information processing device used for debugging, or if the I / O device to be used is not connected, an abnormal termination interrupt occurs. The means for collecting this interrupt and analysis of interrupt information ,
By operating the debug support program having a means for simulating the operation on the architecture and a means for re-execution from the interrupt occurrence location at the same time as the function test program, the operation of the function test program was performed normally. It is characterized by automatic control.

Further, it is also a feature of the debug system using this debug support program that the operator has a means for designating an instruction and an input / output device to be simulated.

[0011]

According to the present invention, the function test program can be debugged easily by using an information processing device which is different from the information processing device to be tested or lacks some functions. This eliminates the need for manual judgment and program patch work, and enables efficient debugging, so that defects that cannot be extracted by an instruction simulator can be extracted before application to verification of an information processing device, and quality can be improved. be able to.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram showing an embodiment of a processing operation according to the present invention of a debugging method of an information processing apparatus functional test program of the present invention, and FIG. 2 is a book of an information processing apparatus used for the execution. It is a block diagram which shows one Example of the structure which concerns on invention.

The information processing apparatus of this embodiment shown in FIG.
The main storage device 21 is connected to the instruction processor 23 and the input / output processor 24 via the storage control device 22, and the input / output processor 24 is provided with the input / output device 27 and the instruction processor 23 is provided with the service device 25. The service processors 26 are connected to each other via the above.

The function test program, the debug support program, and the control program for controlling these programs are stored in the input / output device 27.

In the information processing apparatus having such a configuration, the function test program, the debug support program and the control program are executed by the instruction processor 23.
Further, the service processor 26 issues an execution request for a control program, a function test program, and a debug support program from an operator, an instruction to be simulated, and an instruction of an input / output device.

First, an operator makes a control program execution request using the service processor 26.
The control program stored in the input / output device 27 by the service device 25 is transferred to and stored in the main storage device 21 via the input / output processor 24 and the storage control device 22, and further via the storage control device 22. It is executed in the instruction processor 23, and the preparation for execution of the function test program and the debug support program is completed.

An operator's request for executing the function verification program and the debug support program using the service processor 26 is sent via the service device 25.
The control program operating in the instruction processor 23 receives the function verification program and the debug support program stored in the input / output device 27, and transfers them to the main storage device 21 via the input / output processor 24 and the storage control device 22. And store. Further, the stored function test program and debug support program are stored in the storage controller 2
2 through the instruction processor 23.

Further, the control program operating in the instruction processor 23 receives via the service device 25 the instruction to be simulated and the instruction of the input / output device by the operator using the service processor 26, and the same as the control program. By reporting to the debug support program operating in the instruction processor 23, the instruction to be simulated and the input / output device are registered.

The operation of the real machine debugging method of the information processing apparatus of this embodiment will be described below with reference to the flowchart of FIG.

First, the control program 16 receives a request to start the debug support program from the operator, and generates the debug support program task 11. The task control program task 12 of the control program controls the time-sharing by the time-sharing common bus 17 via the interrupt processing 15.

In this way, after the execution request acceptance processing and the execution processing of the debug support program are performed, the control according to the present invention described below is performed.

That is, the debug support program task 11 switches the interrupt vector 19 when the abnormal end interrupt occurs to the vector 1a indicating the abnormal end interrupt collection process 14 of the debug support program in the interrupt vector switching process 1b. Then, when the initial preparation for the debug support is completed, an initial preparation completion message is displayed. The details of this process will be described later with reference to FIG.

Next, the operator confirms the message of the initial preparation completion by the interrupt vector switching process 1b of the debug support program task 11, and then requests the registration of the simulation target item for each function test program task. The control program 16 accepts and reports to the debug support program task 11.

Debug support program task 1
1 performs registration / deletion of the simulation target item for each functional test program task by the simulation target item registration process 1c, and displays a registration or deletion completion message when the registration / deletion process is completed. The details of this process will be described later with reference to FIG. An example of the items to be simulated is shown in FIG.

Thus, the debug environment setting of the function verification program is completed.

Next, when the operator confirms the message of registration or deletion completion by the simulation target item registration / deletion process 1c of the debug support program task 11, and then makes a request to start the function test program, it controls this. The program 16 receives and generates the function test program task 12. As with the debug support program task 11, this task is also time-shured by the time-shuring common bus 17 via the interrupt processing 15 in the task control program task 12 of the control program.

Here, in the function test program task 13, when the unsupported instruction 18 of the information processing apparatus 1h is issued, an abnormal end interrupt is generated, but the abnormal end interrupt collection processing 14 collects this interrupt and generates an interrupt. To the debug support program task 11.

At this time, the debug support program task 11 judges in the simulation target judgment processing 1d whether or not the interrupt content is the simulation target item designated by the operator. The details of this process will be described later with reference to FIG.

If it is determined in the simulation target determination process 1d that the item is a simulation target item, the operation of the abnormally terminated instruction is simulated by the simulation process 1e. The details of this execution process will be described later with reference to FIG. 7.

After completion of the simulation processing by the simulation processing 1e, the abnormal end interrupt collection processing 14
And the bus 1 for restarting the task 13 of the functional test program
The function test program task 13 is restarted via f.

When it is judged in the simulation target judgment processing 1d that it is not the simulation target, the debug support program task 11 reports to the interrupt processing 15 via the abnormal end interrupt collection processing 14 and the bus 1g.

Then, the control program 16 that has received the interrupt by the interrupt processing 15 displays a message for reporting to the operator that an unexpected abnormal end interrupt has occurred, and executes the function test program task deletion processing.

In this way, even if an unsupported instruction of the information processing device is issued in the function test program and an abnormal end interrupt occurs, the debug support program collects the interrupt, simulates the operation of the instruction, and restarts the function test program. By automatically performing, it is possible to easily and efficiently debug a functional test program that uses an information processing device that differs from the information processing device that is the test target, or an information processing device that lacks some functions. In addition, it is possible to guarantee the conventional control for the abnormal termination interrupt that is not expected at all.

Next, the details of the execution processing operation of FIG. 1 will be described with reference to FIGS.

FIG. 3 is a flow chart showing an embodiment of the operation relating to interrupt vector switching when the abnormal end interrupt in FIG. 1 occurs.

In this embodiment, the interrupt vector switching process 1b of the debug support program task 11 in FIG.
First, the interrupt vector 19 set by the control program 16 in FIG. 1 is saved (step 31), and a new abnormal end interrupt collection process 14 of the debug support program task 11 is shown. The interrupt vector 1a is set (step 32). Then, the completion of the initial preparation by the interrupt vector switching process is reported to the operator by a message (step 33). After this, this process repeats waiting for an interrupt for abnormal termination (step 34) and repeats until the operator issues a termination request for the debug support program task via the control program 16 (step 35).

FIG. 4 is a flow chart showing an embodiment of the operation relating to the registration / deletion of the instruction to be simulated and the input / output device in FIG.

This embodiment shows the details of the processing operation of the simulation target item registration / deletion processing 1c in FIG. 1. First, the data input by the operator is analyzed (step 41), and the input is judged to be invalid. Judgment (Step 4
In the case of 2), an input invalid message is displayed (step 43), and the process ends. When it is judged that the input data is correct (step 42), it is judged whether it is common to all tasks or specific task (step 4).
4) If all tasks are common, a common table pointer for all tasks is set (step 45). In the case of the specific task designation, the pointer of the test target item table according to the task of the designated functional test program is set (step 46), and when the operator's designation is the registration designation (step 47), the table pointer is set. The simulation target item is registered in the table shown by (step 48), the registration completion message is displayed (step 49), and then the process ends. When the operator designates deletion (step 47), the designated item is deleted from the table indicated by the table pointer (step 4a), a deletion completion message is displayed (step 4b), and the process is terminated.

FIG. 5 is a table showing an example of data contents related to the registration of the instruction and the input / output device to be simulated in FIG.

This table shows the details of the items that can be requested for the simulation target item registration processing 1c in FIG. 1, and is intended for all function verification program tasks.
All task / unique task type 51 that specifies whether a specific task is targeted, functional test program task type 52 that specifies which task to support for debugging when a specific task is specified, and a simulation A target instruction type 53, an interrupt address range 54 that specifies a simulation target instruction address range, and an interrupt type 55 that specifies a simulation target depending on the type of abnormal termination.
And the input / output device type 56 for specifying the input / output device to be simulated can be specified.

FIG. 6 is a flow chart showing an embodiment of the operation relating to the processing for determining whether or not the interrupt for abnormal termination in FIG. 1 is a simulation target.

This embodiment shows the details of the processing operation of the simulation target judgment processing 1d in FIG. 1. First, based on the interrupt information collected by the abnormal end interrupt collection processing 14 in FIG. The simulation target item table common to the tasks is referred to (step 61), and it is determined whether or not it is a simulation target (step 6).
2). As a result, when it is determined that the interrupt is not the simulation target, the simulation target item table specific to the abnormally ended function test program task is referred to (step 63), and it is determined whether or not it is the simulation target (step 63). If it is determined in step 64) that this result is not the simulation target interrupt, the non-simulation return information is set (step 65), and the process ends.

Further, the simulation target item table peculiar to the function test program task which is common to all the tasks or abnormally ended is referred to (steps 61 and 63), and it is determined whether or not the target is a simulation target (step 62). , 6
4) As a result, if it is determined that the interrupt is a simulation target, the return information of the simulation target is set (step 66), and the process is terminated.

FIG. 7 is a flow chart showing an embodiment of the operation relating to the simulation processing of the instruction operation in which the interrupt of abnormal termination in FIG. 1 has occurred.

This embodiment shows the details of the processing operation of the simulation processing 1e in FIG.
The interrupt instruction is determined from the interrupt address, the interrupt type code, etc., which are the interrupt information collected by the abnormal end interrupt collection processing 14 in step (step 71), and the instruction code of the interrupt instruction, the operand address, and the main memory indicated by the operand address. The contents of the device are analyzed (step 72), and the interrupted instruction is simulated according to the architectural operation (step 73). If the simulation ends normally (step 74), the simulation result is set in the main storage device, register, or the like for the instruction that ended abnormally (step 75), and the return information indicating normal end is set (step 75). 76), and the process ends.

As a result of executing the simulation (step 73), if the simulation does not end normally (step 74), return information for abnormal end is set (step 77), and the process ends.

As described above with reference to FIGS. 1 to 7, in the debugging method of the information processing apparatus function test program of the present embodiment, the debugging of the function verification program uses an information processing apparatus different from the test target. Solve problems such as abnormal termination interrupts that occur in some cases.

As a result, wasteful work such as investigation of the cause of the abnormal end occurrence by the operator and program patch work for avoiding the abnormal end can be eliminated, and the function verification program can be debugged with high efficiency.

The embodiment described with reference to FIGS. 1 to 7 is shown as an example of the present invention.
It is not limited to these examples.

[0051]

According to the present invention, an abnormal end interrupt that occurs when a functional test program is debugged using an information processing device different from the test target is automatically collected and simulated, and normal Since it can be executed as if it operated, it does not require manual judgment or program patch work, and efficient debugging is possible. This allows
It is possible to shorten the debug period of the functional test program and improve the quality.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of a processing operation according to the present invention of a debugging method of an information processing device function test program.

2 is a block diagram showing an embodiment of a configuration according to the present invention of an information processing apparatus used for implementing a debugging method of an information processing apparatus function test program in FIG.

FIG. 3 is a flowchart showing an embodiment of an operation relating to interrupt vector switching when an abnormal end interrupt in FIG. 1 occurs.

FIG. 4 is a flowchart showing an embodiment of an operation relating to registration / deletion of an instruction to be simulated and an input / output device in FIG.

5 is a table showing an example of data content related to registration of an instruction to be simulated and an input / output device in FIG.

FIG. 6 is a flowchart showing an example of an operation relating to a determination process as to whether or not the abnormal termination interrupt in FIG. 1 is a simulation target.

7 is a flowchart showing an example of an operation relating to a simulation process of an instruction operation in which an interrupt for abnormal termination in FIG. 1 has occurred.

[Explanation of symbols]

 11 ... Debug support program task, 12 ... Task control program task, 13 ... Functional test program task, 14 ... Abnormal end interrupt collection processing, 15 ... Interrupt processing, 16 ... Control program, 17 ... Time-sharing common bus, 1h ... Information Processing device, 21 ... Main storage device, 22 ... Storage control device, 23 ... Instruction processor, 24 ... Input / output processor, 25 ... Service device, 26 ... Service processor, 27 ... Input / output device.

Claims (1)

[Claims] 1. At least one or more instruction processors,
Verification of the operation of the information processing device including a peripheral device group such as a main memory device and an input / output device connected to the processor by loading a function test program into the main memory device and causing the instruction processor to execute the program. In the function test method, an unsupported instruction is issued or an input / output device is specified when the function test program is debugged using an information processing device different from the information processing device to be tested by the function test program. Regarding abnormal termination due to, for example, means for collecting an abnormal termination interrupt, means for simulating the abnormally terminated instruction and the architectural operation of the input / output device, and means for automatically re-executing from the interrupt occurrence point Is provided to enable normal execution of the functional test program, which facilitates debugging. Tsu grayed system.